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參數(shù)資料
| 型號： | 933860310602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALS SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 180K |
| 代理商： | 933860310602 |
Philips Semiconductors
Product specification
74ALS573B/74ALS574A
Latch/flip-flop
74ALS573B
Octal transparent latch (3-State)
74ALS574A
Octal D flip-flop (3-State)
2
1991 Feb 08
853–1307 01670
FEATURES
74ALS573B is broadside pinout version of 74ALS373
74ALS574A is broadside pinout version of 74ALS374
Inputs and outputs on opposite side of package allow easy
interface to microprocessors
Useful as an input or output port for microprocessors
3-State outputs for bus interfacing
Common output enable
74ALS563A and 74ALS564A are inverting version of 74ALS573B
and 74ALS574A respectively
DESCRIPTION
The 74ALS573B is an octal transparent latch coupled to eight
3-State output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The 74ALS573B is functionally identical to the 74ALS373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the data that is present one setup
time before the High-to-Low enable transition.
The 74ALS574A is functionally identical to the 74ALS374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
It is an 8-bit edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, latched or
transparent data appears at the output.
When OE is High, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS573B
5.0ns
12mA
74ALS574A
6.0ns
15mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
DRAWING
NUMBER
20-pin plastic DIP
74ALS573BN, 74ALS574AN
SOT146-1
20-pin plastic SOL
74ALS573BD, 74ALS574AD
SOT163-1
20-pin plastic SSOP
Type II
74ALS573BDB,
74ALS574ADB
SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 – D7
Data inputs
1.0/1.0
20
A/0.2mA
E (74ALS573B)
Latch enable input
1.0/1.0
20
A/0.1mA
OE
Output Enable input (active-Low)
1.0/1.0
20
A/0.1mA
CP (74ALS574A)
Clock pulse input (active rising edge)
1.0/2.0
20
A/0.2mA
Q0 – Q7
Data outputs
130/240
2.6mA/24mA
NOTE:
One (1.0) ALS unit load is defined as: 20
A in the High state and 0.1mA in the Low state.
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