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參數(shù)資料
| 型號(hào)： | 933861310623 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 91K |
| 代理商： | 933861310623 |
Philips Semiconductors
Product specification
74F113
Dual J-K negative edge-triggered flip-flops
without reset
2
1996 Mar 14
853–0339 16575
FEATURE
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F113, dual negative edge-triggered JK-type flip-flop, features
individual J, K, clock (CP), set (SD) inputs, true and complementary
outputs. The asynchronous SD input, when low, forces the outputs
to the steady state levels as shown in the function table regardless
of the level at the other inputs.
A high level on the clock (CP) input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs may be
allowed to change while the CP is high and flip-flop will perform
according to the function table as long as minimum setup and hold
times are observed. Output changes are initiated by the high-to-low
transition of the CP.
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
VCC
SD1
Q1
J1
CP1
K1
CP0
K0
Q0
J0
SD0
Q0
SF00140
TYPE
TYPICAL fmax
TYPICAL SUPPLY CURRENT (TOTAL)
74F113
100MHz
15mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
INDUSTRIAL RANGE
VCC = 5V ±10%,
Tamb = –40°C to +85°C
PKG. DWG. #
14-pin plastic DIP
N74F113N
I74F113N
SOT27–1
14-pin plastic SO
N74F113D
I74F113D
SOT108–1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
J0, J1
J inputs
1.0/1.0
20
A/0.6mA
K0, K1
K inputs
1.0/1.0
20
A/0.6mA
CP0, CP1
Clock inputs (active falling edge)
1.0/4.0
20
A/2.4mA
SD0, SD1
Set inputs (active low)
1.0/5.0
20
A/3.0mA
Q0, Q1, Q0, Q1
Data outputs
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
Q0
Q1
56
98
VCC = Pin 14
GND = Pin 7
1
4
13
10
CP0
SD0
CP1
SD1
J1
K0
212
SF00141
K1
J0
311
IEC/IEEE SYMBOL
3
1
2
4
11
13
12
10
5
6
9
8
1J
2J
C1
C2
1S
1K
2K
2S
SF00142
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