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參數(shù)資料
| 型號(hào)： | 933876860602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-38-4, DIP-16 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 88K |
| 代理商： | 933876860602 |
Philips Semiconductors
Product specification
74F173
Quad D-type flip–flop (3-State)
2
August 31, 1990
853–1160 00286
FEATURES
Edge–triggered D–type register
Gated clock enable for hold ”do nothing” mode
3–state output buffers
Gated output enable control
Speed upgrade of N8T10 and current sink upgrade
Controlled output edges to minimize ground bounces
48mA sinking capability
DESCRIPTION
The 74F173 is a high speed 4–bit parallel load register with
clock enable control, 3–state buffered outputs, and master
reset (MR). When the two clock enable (E0 and E1) inputs
are low, the data on the D inputs is loaded into the register
simultaneously with low–to–high clock (CP) transition. When
one or both enable inputs are high one setup time before the
low–to–high clock transition, the register retains the previous
data.
Data inputs and clock enable inputs are fully edge–triggered
and must be stable only one setup time before the
low–to–high clock transition.
The master reset (MR) is an active–high asynchronous
input. When the MR is high, all four flip–flops are reset
(cleared) independently of any other input condition.
The 3–state output buffers are controlled by a 2–input NOR
gate. When both output enable (OE0 and OE1) inputs are
low, the data in the register is presented at the Q output.
When one or both OE inputs are high, the outputs are forced
to a high impedance ”off” state.
The 3–state output buffers are completely independent of
the register operation; the OE transition does not affect the
clock and reset operations.
TYPE
TYPICAL fmax
TYPICAL SUPPLY CURRENT (TOTAL)
74F173
125MHz
23mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
PKG DWG #
16–pin plastic DIP
N74F173N
SOT38-4
16–pin plastic SO
N74F173D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOW
LOAD VALUE
HIGH/LOW
D0 – D3
Data inputs
1.0/1.0
20
A/0.6mA
CP
Clock input
1.0/1.0
20
A/0.6mA
E0, E1
Clock enable inputs
1.0/1.0
20
A/0.6mA
MR
Master reset input
1.0/1.0
20
A/0.6mA
OE0, OE1
Output enable inputs
1.0/1.0
20
A/0.6mA
Q0 – Q3
Data outputs
750/80
15mA/48mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20
A in the high state and 0.6mA in the low state.
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