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參數(shù)資料
| 型號： | 934055222118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | 48 A, 25 V, 0.018 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | PLASTIC, DPAK-3 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 145K |
| 代理商： | 934055222118 |
Philips Semiconductors
Product specification
N-channel TrenchMOS
transistor
PHP50N03LT, PHB50N03LT
Logic level FET
PHD50N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
’Trench’ technology
V
DSS = 25 V
Very low on-state resistance
Fast switching
I
D = 48 A
High thermal cycling performance
Low thermal resistance
R
DS(ON) ≤ 16 m (VGS = 10 V)
Logic level compatible
R
DS(ON) ≤ 21 m (VGS = 5 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
High frequency computer motherboard d.c. to d.c. converters
High current switching
The PHP50N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB50N03LT is supplied in the SOT404 (D
2PAK) surface mounting package.
The PHD50N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404 (D
2PAK)
SOT428 (DPAK)
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DSS
Drain-source voltage
T
j = 25 C to 175C
-
25
V
DGR
Drain-gate voltage
T
j = 25 C to 175C; RGS = 20 k
-25
V
GS
Gate-source voltage (DC)
-
± 15
V
GSM
Gate-source voltage (pulse
T
j ≤ 150C
-
± 20
V
peak value)
I
D
Drain current (DC)
T
mb =
25 C
-
48
A
T
mb = 100 C
-
34
A
I
DM
Drain current (pulse peak
T
mb = 25 C
-
180
A
value)
P
tot
Total power dissipation
T
mb = 25 C
-
86
W
T
j, Tstg
Operating junction and
- 55
175
C
storage temperature
d
g
s
12 3
tab
13
tab
2
1
2
3
tab
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
October 1999
1
Rev 1.800
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