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參數(shù)資料
| 型號(hào)： | 934055514115 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 1.3 A BUF OR INV BASED PRPHL DRVR, PDSO4 |
| 封裝： | PLASTIC, SC-73, SOT-223, 4 PIN |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 66K |
| 代理商： | 934055514115 |
Philips Semiconductors
Product specification
PowerMOS transistor
BUK127-50DL
Logic level TOPFET
OUTPUT CHARACTERISTICS
Limits are for -40C
≤ T
mb ≤ 150C; typicals are for Tmb = 25 C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Off-state
V
IS = 0 V
V
(CL)DSS
Drain-source clamping voltage
I
D = 10 mA
50
-
V
I
D = 200 mA; tp ≤ 300 s; δ ≤ 0.01
50
60
70
V
I
DSS
Drain source leakage current
V
DS = 40 V
-
100
A
T
mb = 25 C
-
0.1
10
A
On-state
V
IS ≥ 4 V; tp ≤ 300 s; δ ≤ 0.01
R
DS(ON)
Drain-source resistance
I
D = 100 mA
-
380
m
T
mb = 25 C
-
150
200
m
INPUT CHARACTERISTICS
The supply for the logic and overload protection is taken from the input.
Limits are for -40C
≤ T
mb ≤ 150C; typicals are for Tmb = 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
IS(TO)
Input threshold voltage
V
DS = 5 V; ID = 1 mA
0.6
-
2.4
V
T
mb = 25C
1.1
1.6
2.1
V
I
IS
Input supply current
normal operation;
V
IS = 5 V
100
220
400
A
V
IS = 4 V
80
195
330
A
I
ISL
Input supply current
protection latched;
V
IS = 5 V
200
400
650
A
V
IS = 3 V
130
250
430
A
V
ISR
Protection reset voltage
1
reset time t
r ≥ 100 s
1.5
2
2.9
V
t
lr
Latch reset time
V
IS1 = 5 V, VIS2 < 1 V
10
40
100
s
V
(CL)IS
Input clamping voltage
I
I = 1.5 mA
5.5
-
8.5
V
R
IG
Input series resistance
2
T
mb = 25C
-
33
-
k
to gate of power MOSFET
1 The input voltage below which the overload protection circuits will be reset.
2 Not directly measureable from device terminals.
October 2001
3
Rev 1.011
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