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參數(shù)資料
| 型號： | 934056845115 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 1.3 A BUF OR INV BASED PRPHL DRVR, PDSO4 |
| 封裝： | PLASTIC, SC-73, SOT-223, 4 PIN |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 59K |
| 代理商： | 934056845115 |
Philips Semiconductors
Product specification
PowerMOS transistor
PIP3103-T
Logic level TOPFET
Fig.14. Typical Protection reset voltage.
V
ISR = f(Tj); tlr = 100 s.
Fig.15. Overvoltage clamping characteristic, 25C.
I
D = f(VDS); conditions: VIS = 0 V; tp ≤ 300 s
Fig.16. Test circuit for resistive load switching times.
V
IS = 5 V
Fig.17. Typical switching waveforms, resistive load .
R
L = 50 ; adjust VDD to obtain ID = 250 mA; Tj = 25C
Fig.18. Typical drain source leakage current
I
DSS = f(Tj); conditions: VDS = 40 V; VIS = 0 V.
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
-50
50
150
VISR / V
Tj / C
-25
0
25
75
100
125
VIS
VDS
0
5
10
15
-20
20
40
60
80
100
120
140
160
0
-40
time / us
VIS & VDS / V
56
58
60
62
64
66
68
0
100
200
300
400
ID / mA
VDS / V
TYP.
-50
0
50
100
150
10 uA
1 uA
100 nA
10 nA
IDSS
Tj / C
VDD
D.U.T.
0V
VIS
D
S
I
TOPFET
P
RL
VDS
measure
June 2001
7
Rev 1.000
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