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參數(shù)資料
| 型號： | 935007670118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 105K |
| 代理商： | 935007670118 |
Philips Semiconductors
Product specification
74F50729
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
1990 Sep 14
5
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’
78910
1012
1011
1010
109
108
107
106
1014
1015 = fCfI
t’ in nanoseconds
MTBF in seconds
one year
106
108
1010
1012
one week
10,000 years
100 years
SF00589
NOTE: VCC = 5V, Tamb = 25°C, τ =135ps, To = 9.8 X 106 sec
Figure 4.
TYPICAL VALUES FOR
τ AND T0 AT VARIOUS VCCS AND TEMPERATURES
Tamb = 0°C
Tamb = 25°C
Tamb = 70°C
VCC
τ
T0
τ
T0
τ
T0
5.5V
125ps
1.0 X 109 sec
138ps
5.4 X 106 sec
160ps
1.7 X 105 sec
5.0V
115ps
1.3 X 1010 sec
135ps
9.8 X 106 sec
167ps
3.9 X 104 sec
4.5V
115ps
3.4 X 1013 sec
132ps
5.1 X 108 sec
175ps
7.3 X 104 sec
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
SD
RD
CP
D
Q
MODE
↑
X
H
L
Asynchronous set
↑
X
L
H
Asynchronous reset
↑
h
H
L
Load ”1”
↑
l
L
H
Load ”0”
↑
X
NC
Hold
NOTES:
1. H = High–voltage level
2. h
= High–voltage level one setup time prior to low–to–high clock
transition
3. L
= Low–voltage level
4. l
= Low–voltage level one setup time prior to low–to–high clock
transition
5. NC= No change from the previous setup
6. X = Don’t care
7.
↑ = Low–to–high clock transition
8.
↑ = Not low–to–high clock transition
LOGIC DIAGRAM
VCC = Pin 14
GND = Pin 7
4, 10
3, 11
SD
CP
Q
5, 9
SF00614
2, 12
D
1, 13
RD
6, 8
Q
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