參數(shù)資料
型號: 935008910118
廠商: NXP SEMICONDUCTORS
元件分類: 無繩電話/電話
英文描述: TELEPHONE MULTIFUNCTION CKT, PDSO16
封裝: 7.50 MM, PLASTIC, SOT-162-1, MS-013AA, SO-16
文件頁數(shù): 6/32頁
文件大?。?/td> 253K
代理商: 935008910118
1996 Nov 21
14
Philips Semiconductors
Product specication
DTMF/modem/musical-tone generators
PCD3311C; PCD3312C
Table 6
Explanation of time symbols used in Fig.11
8.5.2
LOW-SPEED MODE
Masters generate a bus clock with a maximum frequency of 2 kHz; a minimum LOW period of 105
s and a minimum
HIGH period of 365
s. The mark-to-space ratio is 1 : 3 LOW-to-HIGH. Detailed timing is shown in Fig.13, where the two
signal levels are LOW = VIL and HIGH = VIH, see Chapter 11. Figure 14 shows a complete data transfer in low-speed
mode.The time symbols are explained in Table 7.
SYMBOL
PARAMETER
REMARKS
MIN.
MAX.
UNIT
fSCL
SCL clock frequency
0
100
kHz
tSW
tolerable pulse spike width
100
ns
tBUF
bus free time
The time that the bus is free (SDA is HIGH)
before a new transmission is initiated by SDA
going LOW.
4.7
s
tSU;STA
set-up time repeated START
Only valid for repeated start code.
4.7
s
tHD;STA
hold time START condition
The time between SDA going LOW and the rst
valid negative-going transition of SCL.
4.0
s
tLOW
SCL LOW time
The LOW period of the SCL clock.
4.7
s
tHIGH
SCL HIGH time
The HIGH period of the SCL clock.
4.0
s
tr
rise time SDA and SCL
1.0
s
tf
fall time SDA and SCL
0.3
s
tSU;DAT
data set-up time
250
ns
tHD;DAT
data hold time
0
ns
tSU;STO
set-up time STOP condition
4.0
s
Fig.12 Complete data transfer in standard mode.
handbook, full pagewidth
MBC765
9
8
1 - 7
9
8
1 - 7
9
8
1 - 7
STOP
ACK
ADDRESS
R/W
START
CONDITION
ACK
DATA
START
CONDITION
ACK
ADDRESS
R/W
SCL
SDA
Clock LOW minimum = 4.7
s; clock HIGH minimum = 4 s.
The dashed line is the acknowledgment of the receiver.
Mark-to-space ratio = 1 : 1 (LOW-to-HIGH).
Maximum number of bytes is unrestricted.
Premature termination of transfer is allowed by generation of STOP condition.
Acknowledge clock bit must be provided by master.
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