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參數(shù)資料
| 型號(hào)： | 935012870112 |
| 廠(chǎng)商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 諧振器 |
| 英文描述： | PRESCALER, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 92K |
| 代理商： | 935012870112 |
June 1986
3
Philips Semiconductors
Product specication
Sensitive 1 GHz divide-by-64/divide-by-256
switchable prescaler
SAB6456
SAB6456T
Fig.2 Pinning diagram.
PINNING
1.
n.c.
not connected
2.
C1
differential inputs
3.
C2
4.
VEE
ground (0 V)
5.
MC
mode control
6.
QH
complementary outputs
7.
QL
8.
VCC
positive supply voltage
FUNCTIONAL DESCRIPTION
The circuit comprises an input amplifier, a divider stage with selectable division ratio and an output stage.
The input amplifier is driven by a sinusoidal signal from the local oscillator of a television tuner. The inputs (C1, C2) are
differential and are biased internally to permit capacitive coupling. When driven asymmetrically the unused input should
be connected to ground via a capacitor.
The mode-control (MC) input to the divider stage is intended for static control of the division ratio, selection is made as
follows:
divide-by-64: MC pin open-circuit
divide-by-256: MC pin connected to ground
The divider stage may oscillate during no-signal conditions but this oscillation is suppressed when input signals are
received.
Two complementary signals (QH, QL) are provided by the output differential amplifier stage. The voltage-edges of the
output signals are slowed internally to reduce harmonics in the television intermediate frequency band.
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