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參數(shù)資料
| 型號(hào)： | 935025650623 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 鎖存器 |
| 英文描述： | F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SO-16 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 93K |
| 代理商： | 935025650623 |
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
2
February 9, 1990
853–0338 98775
FEATURE
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop,
feature individual J, K, Clock (CPn), Set (SD) and Reset (RD)
inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown
in the Function Table, regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs may be
allowed to change while the CPn is High and flip-flop will perform
according to the Function Table as long as minimum setup and hold
times are observed. Output changes are initiated by the High-to-Low
transition of the CPn.
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
Q1
VCC
K1
J1
SD1
CP1
RD0
RD1
CP0
K0
Q0
J0
SD0
Q0
9
8
GND
Q1
SF00103
TYPE
TYPICAL PROPAGATION DELAY
TYPICAL SUPPLY CURRENT (TOTAL)
74F112
100MHz
15mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
INDUSTRIAL RANGE
VCC = 5V ±10%, Tamb = –40°C to +85°C
PKG DWG #
16-pin plastic DIP
N74F112N
I74F112N
SOT38-4
16-pin plastic SO
N74F112D
I74F112D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
J0, J1
J inputs
1.0/1.0
20
A/0.6mA
K0, K1
K inputs
1.0/1.0
20
A/0.6mA
SD0, SD1
Set inputs (active Low)
1.0/5.0
20
A/3.0mA
RD0, RD1
Reset inputs (active Low)
1.0/5.0
20
A/3.0mA
CP0, CP1
Clock Pulse input (active falling edge)
1.0/4.0
20
A/2.4mA
Q0, Q0; Q1, Q1
Data outputs
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
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