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參數(shù)資料
| 型號(hào)： | 935039720118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SO-16 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 76K |
| 代理商： | 935039720118 |
Philips Semiconductors
Product specification
74F379A
Quad register
2
1996 Mar 12
853-0027 16555
FEATURES
Edge–triggered D–type inputs
Buffered positive edge–triggered clock
Buffered common enable input
True and complementary outputs
Offers light loading PNP inputs (I
IL = –20A)
DESCRIPTION
The 74F379A is a 4–bit register with buffered common
enable (E). This device is similar to the 74F175A but
features the common enable rather than common master
reset.
TYPE
TYPICAL fmax
TYPICAL SUPPLY CURRENT (TOTAL)
74F379A
200MHz
29mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
PKG, DWG. #
16–pin plastic DIP
N74F379AN
SOT38–4
16–pin plastic SO
N74F379AD
SOT109–1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
TYPE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOW
LOAD VALUE
HIGH/LOW
D0 – D3
Data inputs
1.0/0.033
20
A/20A
74F379A
CP
Clock pulse input (active rising edge)
1.0/0.033
20
A/20A
E
Enable input (active low)
1.0/0.033
20
A/20A
Q0 – Q3
True outputs
50/33
1.0mA/20mA
Q0 – Q3
Complementary outputs
50/33
15mA/20mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20
A in the high state and 0.6mA in the low state.
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
9
8
SF00354
E
Q0
D0
D1
Q1
GND
VCC
Q3
D3
D2
Q2
CP
LOGIC SYMBOL
VCC = Pin 16
GND = Pin 8
SF00355
4
5
12
13
D0 D1 D2 D3
9
1
CP
E
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
3
2
6
7
11 10 14
15
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