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參數(shù)資料
| 型號： | 935040280602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | BUS ARBITER AND CONT SIG GEN, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-38-4, DIP-16 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 105K |
| 代理商： | 935040280602 |
Philips Semiconductors
Product specification
74F786
4-bit asynchronous bus arbiter
2
February 14, 1991
853–1269 01717
FEATURES
Arbitrates between 4 asynchronous inputs
Separate grant output for each input
Common output enable
On board 4 input AND gate
Metastable–free outputs
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F786 is an asynchronous 4–bit arbiter designed for high
speed real–time applications. The priority of arbitration is determined
on a first–come first–served basis. Separate bus grant (BGn)
outputs are available to indicate which one of the request inputs is
served by the arbitration logic. All BGn outputs are enabled by a
common enable (EN) pin. In order to generate a bus request signal
a separate 4 input AND gate is provided which may also be used as
an independent AND gate. Unused bus request (BR) inputs may be
disabled by tying them high.
The 74F786 is designed so that contention between two or more
request signals will not glitch or display a metastable condition. In
this situation an increase in the BRn to BGn tPHL may be observed.
A typical 74F786 has an h = 6.6ns, t = 0.41ns and To = 5
sec.
Where:
h = Typical propagation delay through the device and t and To are
device parameters derived from test results and can most nearly be
defined as:
t = A function of the rate at which a latch in a metastable state
resolves that condition.
To = A function of the measurement of the propensity of a latch to
enter a metastable state. To is also a very strong function of the
normal propagation delay of the device.
For further information, please refer to the 74F786 application notes.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F786
6.6ns
55mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
INDUSTRIAL RANGE
DESCRIPTION
VCC = 5V ±10%,
PKG DWG #
Tamb = 0°C to +70°C
Tamb = –40°C to +85°C
16–pin plastic DIP
N74F786N
I74F786N
SOT 38-4
16–pin plastic SO
N74F786D
I74F786D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOW
LOAD VALUE HIGH/
LOW
BR0 – BR3
Bus request inputs (active low)
1.0/3.0
20
A/1.8mA
A, B, C, D
AND gate inputs
1.0/1.0
20
A/0.6mA
EN
Common bus grant output enable input (active low)
1.0/1.0
20
A/0.6mA
YOUT
AND gate output
150/40
3.0mA/24mA
BG0 – BG3
Bus grant outputs (active low)
150/40
3.0mA/24mA
NOTE:
One (1.0) FAST unit load is defined as: 20
A in the high state and 0.6mA in the low state.
LOGIC SYMBOL
BR0 BR1 BR2 BR3
A
B
C
D
VCC = Pin 16
GND = Pin 8
BG0
BG1
BG2
BG3 YOUT
EN
6
13
12
11
10
14
45
67
15
12
3
SF00442
IEC/IEEE SYMBOL
BUS ARBITER
Φ
74F786
14
9
4
5
6
7
EN
BR0
BR1
BR2
BR3
15
1
2
3
&
13
12
11
10
BG0
BG1
BG2
BG3
SF00443
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