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參數(shù)資料
| 型號： | 935045290602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, OCTAL 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, SOT-137-1, SO-24 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 151K |
| 代理商： | 935045290602 |
Philips Semiconductors
Product specification
74ABT657
Octal transceiver with parity generator/checker
(3-State)
2
1995 Dec 11
853–1615 16106
FEATURES
Combinational functions in one package
Low static and dynamic power dissipation with high speed and
high output drive
Output capability: +64mA/–32mA
Power-up 3-State
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT657 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT657 is an octal transceiver featuring non-inverting buffers
with 3-State outputs and an 8-bit parity generator/checker, and is
intended for bus-oriented applications. The buffers have a
guaranteed current sinking capability of 64mA. The
Transmit/Receive (T/R) input determines the direction of the data
flow through the bidirectional transceivers. Transmit (active-High)
enables data from A ports to B ports; Receive (active-Low) enables
data from B ports to A ports.
The Output Enable (OE) input disables both the A and B ports by
placing them in a high impedance condition when the OE input is
High. The parity select (ODD/EVEN) input gives the user the option
of odd or even parity systems. The parity (PARITY) pin is an output
from the generator/checker when transmitting from the port A to B
(T/R = High) and an input when receiving from port B to A port (T/R
= Low). When transmitting (T/R = High) the parity select
(ODD/EVEN) input is set, then the A port data is polled to determine
the number of High bits. The parity (PARITY) output then goes to the
logic state determined by the parity select (ODD/EVEN) setting and
by the number of High bits on port A. For example, if the parity
select (ODD/EVEN) is set Low (even parity), and the number of
High bits on port A is odd, then the parity (PARITY) output will be
High, transmitting even parity. If the number of High bits on port A is
even, then the parity (PARITY) output will be Low, keeping even
parity. When in receive mode (T/R = Low) the B port is polled to
determine the number of High bits. If parity select (ODD/EVEN) is
Low (even parity) and the number of Highs on port B is:
(1) odd and the parity (PARITY) input is High, then ERROR will be
High, signifying no error.
(2) even and the parity (PARITY) input is High, then ERROR will be
asserted Low, indicating an error.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25°C; GND = 0V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50pF; VCC = 5V
3.3
ns
CIN
Input capacitance
VI = 0V or VCC
4
pF
CI/O
I/O capacitance
Outputs disabled;
VO = 0V or VCC
7
pF
ICCZ
Total supply current
Outputs disabled; VCC =5.5V
500
nA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
24-Pin Plastic DIP
–40
°C to +85°C
74ABT657 N
SOT222-1
24-Pin plastic SO
–40
°C to +85°C
74ABT657 D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°C to +85°C
74ABT657 DB
SOT340-1
24-Pin Plastic TSSOP Type I
–40
°C to +85°C
74ABT657 PW
74ABT657PW DH
SOT355-1
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1OE
ERROR
ODD/EVEN
T/R
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
VCC
A5
A6
A7
PARITY
GND
SA00181
TOP VIEW
PIN DESCRIPTION
SYMBOL
PIN NUMBER
NAME AND FUNCTION
13
PARITY
Parity output
11
ODD/EVEN
Parity select input
12
ERROR
Error output
1
T/R
Transmit/receive input
2, 3, 4, 5,
6, 8, 9, 10
A0 - A7
A port 3-State outputs
23, 22, 21, 20,
17, 16, 15, 14
B0 - B7
B port 3-State outputs
24
OE
Output enable input (active-Low)
18, 19
GND
Ground (0V)
7
VCC
Positive supply voltage
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