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參數(shù)資料
| 型號： | 935047950623 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24 |
| 封裝： | PLASTIC, SO-24 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 97K |
| 代理商： | 935047950623 |
Philips Semiconductors Advanced BiCMOS Products
Product specification
74ABT544
Octal latched transceiver with dual enable,
inverting (3-State)
1
June 1, 1993
853–1610 09907
FEATURES
Combines 74ABT245 and 74ABT373 type
functions in one device
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each
direction
Output capability: +64mA/–32mA
Live insertion/extraction permitted
Power-up 3-State
Power-up reset
Latch-up protection exceeds 500mA per
Jedec JC40.2 Std 17
ESD protection exceeds 2000 V per MIL
STD 883 Method 3015 and 200 V per
Machine Model
DESCRIPTION
The 74ABT544 high-performance BiCMOS
device combines low static and dynamic
power dissipation with high speed and high
output drive.
The 74ABT544 Octal Registered Transceiver
contains two sets of D-type latches for
temporary storage of data flowing in either
direction. Separate Latch Enable (LEAB,
LEBA) and Output Enable (OEAB, OEBA)
inputs are provided for each register to
permit independent control of data transfer in
either direction. The outputs are guaranteed
to sink 64mA.
FUNCTIONAL DESCRIPTION
The ’ABT544 contains two sets of eight
D–type latches, with separate control pins for
each set. Using data flow from A to B as an
example, when the A-to-B Enable (EAB)
input and the A-to-B Latch Enable (LEAB)
input are Low the A-to-B path is transparent.
A subsequent Low-to-High transition of the
LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer
change with the A inputs. With EAB and
OEAB both Low, the 3-State B output buffers
are active and invert the data present at the
outputs of the A latches.
Control of data flow from B to A is similar, but
using the EBA, LEBA, and OEBA inputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
24-pin plastic DIP
–40
°C to +85°C
74ABT544N
0410D
24-pin plastic SOL
–40
°C to +85°C
74ABT544D
0173D
24-pin plastic SSOP Type II
–40
°C to +85°C
74ABT544DB
1641A
PIN CONFIGURATION
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
24
23
22
21
20
19
18
17
16
10
15
9
8
7
6
5
4
3
2
1
VCC
EBA
B0
B1
B2
B3
B4
B5
B6
B7
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
LEBA
21
22
B0 B1 B2
19
20
B3
3
4
5
6
A0 A1 A2 A3
11
23
17
18
B4 B5 B6
15
16
B7
7
8
9
10
A4 A5 A6 A7
EAB
EBA
3
14
12
13
11
LEAB
OEAB
EAB
GND
14
LEAB
1
LEBA
13
OEAB
2
OEBA
11
13
1
23
2
(AB)
(BA)
22
3
4
21
5
20
6
19
7
18
8
17
10
15
9
16
1EN3
G1
1C5
2EN4
G2
2C6
5D
4
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