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參數(shù)資料
| 型號(hào)： | 935063110118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NOR GATE, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, SOT-108-1, MS-012, SO-14 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 139K |
| 代理商： | 935063110118 |
Philips Semiconductors
Product data
74LV02
Quad 2-input NOR gate
2
2003 Mar 03
FEATURES
Wide operating voltage: 1.0 to 5.5 V
Optimized for low voltage applications: 1.0 to 5.5 V
Accepts TTL input levels between V
CC = 2.7 V and VCC = 3.6 V
Typical V
OLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25 °C
Typical V
OHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25 °C
Output capability: standard
I
CC category: SSI
DESCRIPTION
The 74LV02 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT02.
The 74LV02 provides the 2-input NOR function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
nA, nB to nY
CL = 15 pF;
VCC = 3.3 V
6
ns
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per gate
See Notes 1 and 2
22
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in W)
PD = CPD × VCC2 × fi × N + Σ (CL × VCC2 × fo) where:
N = number of outputs switching;
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
PKG. DWG. #
14-Pin Plastic SO
–40
°C to +125 °C
74LV02D
SOT108-1
PIN CONFIGURATION
SV00389
1
2
3
4
5
6
7
1Y
1A
1B
2Y
2A
2B
GND
VCC
4Y
4B
4A
3Y
3B
3A
8
9
10
11
12
13
14
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 4, 10, 13
1Y – 4Y
Data outputs
2, 5, 8, 11
1A – 4A
Data inputs
3, 6, 9, 12
1B – 4B
Data inputs
7
GND
Ground (0 V)
14
VCC
Positive supply voltage
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