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參數(shù)資料
| 型號(hào)： | 935067510623 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, OCTAL 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | PLASTIC, SO-24 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 82K |
| 代理商： | 935067510623 |
Philips Semiconductors
Product specification
74ABT853
8-bit transceiver with 9-bit parity checker/
generator and flag latch (3-State)
1
1995 Sep 06
853-1672 15702
FEATURES
Low static and dynamic power dissipation with high speed and
high output drive
Open-collector ERROR output
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power-up 3-State
Live insertion/extraction permitted
DESCRIPTION
The 74ABT853 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT853 is an octal transceiver with a parity
generator/checker and is intended for bus–oriented applications.
When Output Enable A (OEA) is High, it will place the A outputs in a
high impedance state. Output Enable B (OEB) controls the B
outputs in the same way.
The parity generator creates an odd parity output (PARITY) when
OEB is Low. When OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity. When an error is
detected, the error data is sent to the input of a latch. The error data
can then be passed, stored, cleared, or sampled depending on the
ENABLE and CLEAR control signals.
If both OEA and OEB are Low, data will flow from the A bus to the B
bus and the part is forced into an error condition which creates an
inverted PARITY output. This error condition can be used by the
designer for system diagnostics.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25°C; GND = 0V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50pF; VCC = 5V
3.4
ns
tPLH
tPHL
Propagation delay
An to PARITY
CL = 50pF; VCC = 5V
7.4
ns
CIN
Input capacitance
VI = 0V or VCC
4
pF
CI/O
I/O capacitance
Outputs disabled; VO = 0V or VCC
7
pF
ICCZ
Total supply current
Outputs disabled; VCC =5.5V
50
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
24-Pin Plastic DIP
–40
°C to +85°C
74ABT853 N
SOT222-1
24-Pin plastic SO
–40
°C to +85°C
74ABT853 D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°C to +85°C
74ABT853 DB
SOT340-1
24-Pin Plastic TSSOP Type I
–40
°C to +85°C
74ABT853 PW
74ABT853PW DH
SOT355-1
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
VCC
GND
CLEAR
OEA
B0
B1
B2
B3
B6
B7
PARITY
OEB
A0
A1
A2
A3
A4
A5
A6
A7
ERROR
ENABLE
B4
B5
TOP VIEW
SA00262
LOGIC SYMBOL
OEB
OEA
B0 B1 B2 B3
CLEAR
B4 B5 B6 B7
14
1
11
A0 A1 A2 A3 A4 A5 A6 A7
23
45
67
8
9
23
22
21
20
19
18
17
16
15
10
PARITY
ERROR
ENABLE
13
SA00263
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