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參數(shù)資料
| 型號： | 935069190118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, 10 1-BIT DRIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | PLASTIC, SSOP-24 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 69K |
| 代理商： | 935069190118 |
Philips Semiconductors
Product specification
74ABT821
10-bit D-type flip-flop; positive-edge trigger
(3-State)
1995 Sep 06
5
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Tamb = +25oC
VCC = +5.0V
Tamb = -40 to +85oC
VCC = +5.0V ±0.5V
UNIT
Min
Typ
Min
ts(H)
ts(L)
Setup time, High or Low
Dn to CP
2
2.1
0.5
0.3
2.1
ns
th(H)
th(L)
Hold time, High or Low
Dn to CP
2
1.3
0.0
–0.3
1.3
ns
tw(H)
tw(L)
CP pulse width
High or Low
1
2.9
3.8
1.8
2.8
2.9
3.8
ns
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
VM
tPLH
tPHL
VM
CP
Qn
1/fMAX
tW(H)
tW(L)
SA00159
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
OE
VM
tPZH
tPHZ
0V
Qn
VM
SA00066
VOH–0.3V
Waveform 3. 3–State Output Enable Time to High Level and
Output Disable Time from High Level
VM
Dn
VM
CP
ts(H)
th(H)
ts(L)
th(L)
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SA00107
Waveform 2. Data Setup and Hold Times
OE
tPZL
tPLZ
0V
Qn
VM
SA00067
VOL+0.3V
Waveform 4. 3–State Output Enable Time to Low Level and
Output Disable Time from Low Level
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