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參數(shù)資料
| 型號(hào)： | 935069230112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, OCTAL 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 5.30 MM, PLASTIC, MO-150, SOT-340-1, SSOP2-24 |
| 文件頁(yè)數(shù)： | 7/13頁(yè) |
| 文件大小： | 138K |
| 代理商： | 935069230112 |
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Philips Semiconductors
Product data
74ABT833
Octal transceiver with parity generator/checker
(3-State)
2002 Dec 17
3
LOGIC SYMBOL
OEB
OEA
CLEAR
14
1
11
15
10
PARITY
ERROR
CP
13
23
45
67
89
A0 A1 A2 A3 A4 A5 A6 A7
B0 B1 B2 B3 B4 B5 B6 B7
23 22 21 20 19 18 17 16
SA00213
FUNCTION TABLE
INPUTS
OUTPUTS
MODE
OEB
OEA
An
Σ of Highs
Bn + Parity
Σ of Highs
An
Bn
PARITY
A data to B bus and generate odd parity output
L
H
Odd
Even
(output)
(input)
An
L
H
B data to A bus and check for parity error1
H
L
(output)
X
Bn
(input)
A bus and B bus disabled2
H
X
Z
A data to B bus and generate inverted parity output
L
Odd
Even
(output)
(input)
An
H
L
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When clocked, the error output is LOW if the sum of A inputs is even or HIGH if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
Internal node
Output
MODE
CLEAR
CP
Bn + Parity
Σ of Highs
Point ”P”
Pre–state
ERRORn–1
ERROR
OUTPUT
H
↑
Odd
H
Sample
H
↑
Even
L
X
L
H
X
L
Hold
H
↑
X
NC
Clear
L
X
H
= HIGH voltage level steady state
L
= LOW voltage level steady state
X
= Don’t care
NC = No change
Z
= High impedance “off” state
↑
= LOW-to-HIGH clock transition
↑
= Not a LOW-to-HIGH clock transition
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