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參數(shù)資料
| 型號： | 935085020512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 95/112頁 |
| 文件大小： | 693K |
| 代理商： | 935085020512 |
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1996 Jun 27
83
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xC592
6. Capacitive loads on Port 0 and Port 2 may cause a HIGH level voltage degradation of ALE and PSEN below 0.9VDD
during the address bits are stabilizing.
7. tCY =12tCLK is the machine cycle time.
8. AVREF+ = 5.12 V; AVREF = 0 V; AVDD = 5.0 V.
9. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width.
10. The ADC is monotonic, there are no missing codes.
11. The integral non-linearity (ILe) is the peak difference between the centre of the steps of the actual and the ideal
transfer curve after appropriate adjustment of gain and offset error.
12. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve after
removing gain error, and a straight line which fits the ideal transfer curve. The offset error is constant at every point
of the actual transfer curve.
13. The gain error (Ge) is relative difference in percent between the straight line fitting the actual transfer curve after
removing offset error and the straight line which fits the ideal transfer curve. The gain error is constant at every point
on the transfer curve.
14. The absolute voltage error (Ae) is the maximum difference between the centre of the steps of the actual transfer curve
of the not calibrated ADC and the ideal transfer curve.
15. Not tested during production.
16. Source current for the CTX0, CTX1 outputs together.
Fig.27 Supply current (IDD) as a function of frequency at XTAL1 (fCLK).
(1) Maximum Operating mode (IDD); VDD = 5.5 V
(2) Maximum Operating mode (IDD); VDD = 4.5 V
(3) Maximum Idle and Sleep mode (IDD(IS) ); VDD = 5.5 V
(4) Maximum Idle and Sleep mode (IDD(IS) ); VDD = 4.5 V
handbook, halfpage
04
8
16
50
0
40
MGA172
12
30
20
10
f CLK (MHz)
I DD
(mA)
(1)
(2)
(3)
(4)
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