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參數(shù)資料
| 型號(hào)： | 935085450118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 鎖存器 |
| 英文描述： | F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 100K |
| 代理商： | 935085450118 |
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
2
September 14, 1990
853-1389 00421
FEATURES
Metastable immune characteristics
Output skew less than 1.5ns
See 74F5074 for synchronizing dual D-type flip-flop
See 74F50109 for synchronizing dual J–K positive edge-triggered
flip-flop
See 74F50729 for synchronizing dual dual D-type flip-flop with
edge-triggered set and reset
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F50728 is a cascaded dual positive edge–triggered D–type
featuring individual data, clock, set and reset inputs; also true and
complementary outputs.
Set (SDn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. They set and reset
both flip–flops of a cascaded pair simultaneously. Data must be
stable just one setup time prior to the low–to–high transition of the
clock for guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive–going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output. Data entering the 74F50728 requires two
clock cycles to arrive at the outputs.
The 74F50728 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F50728
are:
τ 135ps and T0 9.8 X 106 sec where τ represents a
function of the rate at which a latch in a metastable state resolves
that condition and To represents a function of the measurement of
the propensity of a latch to enter a metastable state.
TYPE
TYPICAL fmax
TYPICAL SUPPLY
CURRENT (TOTAL)
74F50728
145 MHz
23mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
INDUSTRIAL RANGE
DESCRIPTION
VCC = 5V ±10%,
PKG DWG #
Tamb = 0°C to +70°C
Tamb = –40°C to +85°C
14–pin plastic DIP
N74F50728N
I74F50728N
SOT27-1
14–pin plastic SO
N74F50728D
I74F50728D
SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOW
LOAD VALUE HIGH/
LOW
D0, D1
Data inputs
1.0/0.417
20
A/250A
CP0, CP1
Clock inputs (active rising edge)
1.0/1.0
20
A/20A
SD0, SD1
Set inputs (active low)
1.0/1.0
20
A/20A
RD0, RD1
Reset inputs (active low)
1.0/1.0
20
A/20A
Q0, Q1, Q0, Q1
Data outputs
50/33
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20
A in the high state and 0.6mA in the low state.
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