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| 型號(hào)： | 935143850112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, MO-015AH, SOT-117-1, DIP-28 |
| 文件頁(yè)數(shù)： | 6/34頁(yè) |
| 文件大小： | 313K |
| 代理商： | 935143850112 |
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Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
14
MR1B – Channel B Mode Register 1
MR1B is accessed when the Channel B MR pointer points to MR1.
The pointer is set to MR1 by RESET or by a ‘set pointer’ command
applied via CRB. After reading or writing MR1B, the pointer will
point to MR2B.
MR2B – Channel B Mode Register 2
MR2B is accessed when the Channel B MR pointer points to MR2,
which occurs after any access to MR1B. Accesses to MR2B do not
change the pointer.
The bit definitions for mode registers 1 and 2 are identical to the bit
definitions for MRA and MR2A except that all control actions apply
to the Channel B receiver and transmitter and the corresponding
inputs and outputs.
CSRA – Channel A Clock Select Register
CSRA[7:4] – Channel A Receiver Clock Select
This field selects the baud rate clock for the Channel A receiver as
follows:
CSRA[7:4]
ACR[7] = 0
Baud Rate
ACR[7] = 1
0000
50
75
0001
110
0010
134.5
0011
200
150
0100
300
0101
600
0110
1,200
0111
1,050
2,000
1000
2,400
1001
4,800
1010
7,200
1,800
1011
9,600
1100
38.4k
19.2k
1101
Timer
1110
IP4–16X
1111
IP4–1X
(See also Table 5)
The receiver clock is always a 16X clock except for CSRA[7] = 1111.
CSRA[3:0] – Channel A Transmitter Clock Select
This field selects the baud rate clock for the Channel A transmitter.
The field definition is as per CSR[7:4] except as follows:
CSRA[3:0]
ACR[7] = 0
Baud Rate
ACR[7] = 1
1110
1111
IP3–16X
IP3–1X
IP3–16X
IP3–1X
The transmitter clock is always a 16X clock except for CSR[3:0] =
1111.
CSRB – Channel B Clock Select Register
CSRB[7:4] – Channel B Receiver Clock Select
This field selects the baud rate clock for the Channel B receiver.
The field definition is as per CSRA[7:4] except as follows:
CSRB[7:4]
ACR[7] = 0
Baud Rate
ACR[7] = 1
1110
1111
IP6–16X
IP6–1X
IP6–16X
IP6–1X
The receiver clock is always a 16X clock except for CSRB[7:4] = 1111.
CSRB[3:0] – Channel B Transmitter Clock Select
This field selects the baud rate clock for the Channel B transmitter.
The field definition is as per CSRA[7:4] except as follows:
CSRB[3:0]
ACR[7] = 0
Baud Rate
ACR[7] = 1
1110
1111
IP5–16X
IP5–1X
IP5–16X
IP5–1X
The transmitter clock is always a 16X clock except for CSRB[3:0] =
1111.
CRA – Channel A Command Register
CRA is a register used to supply commands to Channel A. Multiple
commands can be specified in a single write to CRA as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
CRA[7] – Not Used
Should be set to zero for upward compatibility with newer parts.
CRA[6:4] – Channel A Miscellaneous Command
The encoded value of this field may be used to specify a single
command as follows:
CRA[6:4] – COMMAND
000
No command.
001
Reset MR pointer. Causes the Channel A MR pointer to point
to MR1.
010
Reset receiver. Resets the Channel A receiver as if a hard-
ware reset had been applied. The receiver is disabled and
the FIFO is flushed.
011
Reset transmitter. Resets the Channel A transmitter as if a
hardware reset had been applied.
100
Reset error status. Clears the Channel A Received Break,
Parity Error, and Overrun Error bits in the status register
(SRA[7:4]). Used in character mode to clear OE status (al-
though RB, PE and FE bits will also be cleared) and in block
mode to clear all error status after a block of data has been
received.
101
Reset Channel A break change interrupt. Causes the Chan-
nel A break detect change bit in the interrupt status register
(ISR[2]) to be cleared to zero.
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