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參數(shù)資料
| 型號： | 935155040118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24 |
| 封裝： | PLASTIC, SO-24 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 88K |
| 代理商： | 935155040118 |
Philips Semiconductors
Product specification
74ABT651
Octal transceiver/register, inverting (3-State)
1995 Sep 06
3
FUNCTION TABLE
INPUTS
DATA I/O
OPERATING MODE
OEAB
OEBA
CPAB
CPBA
SAB
SBA
An
Bn
OPERATING MODE
L
H
H or L
↑
H or L
↑
X
Input
Isolation
Store A and B data
X
H
↑
H or L
↑
X
**
X
Input
Unspecified
output*
Store A, Hold B
Store A in both registers
L
X
L
H or L
↑
X
**
Unspecified
output*
Input
Hold A, Store B
Store B in both registers
L
X
H or L
X
L
H
Output
Input
Real time B data to A bus
Stored B data to A bus
H
X
H or L
X
L
H
X
Input
Output
Real time A data to B bus
Store A data to B bus
H
L
H or L
H
Output
Stored A data to B bus
Stored B data to A bus
H = High voltage level
L
= Low voltage level
X = Don’t care
↑ = Low-to-High clock transition
*
The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
**
If both Select controls (SAB and SBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must be
staggered in order to load both registers.
LOGIC DIAGRAM
1D
C1
Q
19
18
17
16
15
14
13
B1
B2
B3
B4
B5
B6
B7
5
6
7
8
9
10
11
A1
A2
A3
A4
A5
A6
A7
DETAIL A X 7
OEBA
OEAB
CPBA
SBA
CPAB
SAB
21
3
23
22
1
2
20
B0
1D
C1
Q
4
A0
1of 8 Channels
SA00098
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