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參數(shù)資料
| 型號： | 935170710118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | 5.30 MM, PLASTIC, MO-150, SOT-339-1, SSOP-20 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 111K |
| 代理商： | 935170710118 |
74LVT573_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 15 September 2008
8 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
11. Waveforms
Measurement points are given in Table 8.
Fig 6.
Propagation delays latch enable input (LE) to
output (Qn), and latch enable (LE) pulse width
Fig 7.
Propagation delay data input (Dn) to
output (Qn)
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur
with the output load.
Measurement points are given in Table 8.
Fig 8.
Output enable time to HIGH-state and output
disable time from HIGH-state
Fig 9.
Output enable time to LOW-state and output
disable time from LOW-state
Measurement points are given in Table 8.
Remark: The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 10. Data setup and hold times for data (Dn) and latch enable (LE) inputs
001aai743
LE input
Qn output
tPHL
tPLH
tWH
VM
VOH
VI
0 V
VOL
VM
tWL
001aai742
Dn input
Qn output
tPHL
tPLH
0 V
VI
VM
VOH
VOL
Qn output
001aai745
OE input
VM
VI
VOH
0 V
tPZH
tPHZ
VY
VM
001aai746
tPZL
tPLZ
VM
Qn output
OE input
VI
VOL
3.0 V
VX
0 V
001aai744
th(H)
tsu(L)
th(L)
tsu(H)
VM
VI
0 V
VI
0 V
LE input
Dn input
Table 8.
Measurement points
Input
Output
VM
VX
VY
1.5 V
VOL + 0.3 V
VOH 0.3 V
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