參數(shù)資料
型號(hào): 935176920112
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 畫(huà)面疊加
英文描述: ON-SCREEN DISPLAY IC, PDSO24
封裝: PLASTIC, SOT-137-1, SO-24
文件頁(yè)數(shù): 11/66頁(yè)
文件大小: 445K
代理商: 935176920112
1995 Jan 19
19
Philips Semiconductors
Preliminary specication
Stand-alone OSD
PCA8515
9.4
Command 3
Table 19 Command 3 format
Command 3 loads the DCR Address Register with the
4 MSBs of the RAM address to which data will be written.
9.5
Command 4
Table 20 Command 4 format
Command 4 loads the DCR Address Register with the
4 LSBs of the RAM address to which data will be written.
9.6
Command 5
Table 21 Command 5 format
Command 5 is used to load character data into the DCR
Character Register. The data will specify either a
Character Font Code, the Test Code, the Carriage Return
Code or the Space Code. These codes are explained in
detail in Section 8.1.
9.7
Command 6
Table 22 Command 6 format
Command 6 loads the programmable 6-bit counter of the
OSD clock oscillator. The output frequency (fOSD) is a
function of the decimal value of the 6-bits loaded in by
Command 6. See Chapter 11.
BS1
BS0
76543210
0
1
A7
A6
A5
A4
BS1
BS0
76543210
0
1
A3
A2
A1
A0
BS1
BS0
76543210
1
0
1
C6C5C4C3C2C1C0
BS1
BS0
76543210
0
1
0
D5
D4
D3
D2
D1
D0
9.8
Command 7
Table 23 Command 7 format
This command loads Control Register 1 with data that
selects the scan mode, the output polarity of signals FB,
ACM, R, G, B and I, and also enables/disables the OSD
clock.
Table 24 Selection of Scan Mode
Table 25 Selection of output polarity (see Fig.13)
Table 26 OSD clock control
BS1
BS0
76543210
0
1
0
1
0
M1
M0
Bp
EN
M1
M0
SCAN MODE
0
NTSC - 525LPF/60 Hz or
PAL 625LPF/50 Hz; see Fig.11. This is
the default setting.
0
1
reserved
1
0
reserved
1
PAL 1250LPF/100 Hz - PAL; see
Fig.12.
Bp
OUTPUT POLARITY (FB, ACM, R, G, B, I)
0
active LOW
1
active HIGH (the default setting)
EN
OSD CLOCK
0
disabled (the default setting)
1
enabled
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