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參數(shù)資料
| 型號(hào)： | 935178940118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, OCTAL 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-355-1, TSSOP1-24 |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大?。?/td> | 138K |
| 代理商： | 935178940118 |
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Philips Semiconductors
Product data
74ABT833
Octal transceiver with parity generator/checker
(3-State)
2
2002 Dec 17
FEATURES
Low static and dynamic power dissipation with high speed and
high output drive
Open-collector ERROR output with flag register
Output capability: +64 mA / –32 mA
Latch-up protection exceeds 500 mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power-up/down 3-State
Live insertion/extraction permitted
DESCRIPTION
The 74ABT833 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT833 is an octal transceiver with a parity
generator/checker and is intended for bus-oriented applications.
When Output Enable A (OEA) is HIGH, it will place the A outputs in
a high impedance state. Output Enable B (OEB) controls the B
outputs in the same way.
The parity generator creates an odd parity output (PARITY) when
OEB is LOW. When OEA is LOW, the parity of the B port, including
the PARITY input, is checked for odd parity. When an error is
detected, the error data is sent to the input of a storage register. If a
LOW-to-HIGH transition happens at the clock input (CP), the error
data is stored in the register and the Open-collector error flag
(ERROR) will go LOW. The error flag register is cleared with a LOW
pulse on the CLEAR input.
If both OEA and OEB are LOW, data will flow from the A bus to the
B bus and the part is forced into an error condition which creates an
inverted PARITY output. This error condition can be used by the
designer for system diagnostics.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25 °C; GND = 0 V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50 pF; VCC = 5 V
3.4
ns
tPLH
tPHL
Propagation delay
An to PARITY
CL = 50 pF; VCC = 5 V
7.4
ns
CIN
Input capacitance
VI = 0 V or VCC
4
pF
CI/O
I/O capacitance
Outputs disabled; VO = 0 V or VCC
7
pF
ICCZ
Total supply current
Outputs disabled; VCC = 5.5 V
50
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
PART NUMBER
DWG NUMBER
24-Pin plastic SO
–40
°C to +85 °C
74ABT833D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°C to +85 °C
74ABT833DB
SOT340-1
24-Pin Plastic TSSOP Type I
–40
°C to +85 °C
74ABT833PW
SOT355-1
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
VCC
GND
CLEAR
OEA
B0
B1
B2
B3
B6
B7
PARITY
OEB
A0
A1
A2
A3
A4
A5
A6
A7
ERROR
CP
B4
B5
TOP VIEW
SA00212
PIN DESCRIPTION
SYMBOL
PIN NUMBER
NAME AND FUNCTION
A0 – A7
2, 3, 4, 5,
6, 7, 8, 9
A port 3-State inputs/outputs
B0 – B7
23, 22, 21, 20,
19, 18, 17, 16
B port 3-State inputs/outputs
OEA
1
Enables the A outputs when LOW
OEB
14
Enables the B outputs when LOW
PARITY
15
Parity output/input
ERROR
10
Error output (open collector)
CLEAR
11
Clears the error flag register
when LOW
CP
13
Clock input
GND
12
Ground (0 V)
VCC
24
Positive supply voltage
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