參數(shù)資料
型號： 935182390118
廠商： NXP SEMICONDUCTORS
元件分類： PROM
英文描述： 1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封裝： PLASTIC, SOT-176, SO-8
文件頁數(shù)： 4/27頁
文件大?。?/td> 219K
代理商： 935182390118
1997 Feb 13
12
Philips Semiconductors
Product specication
256 to 1024
× 8-bit CMOS EEPROMs with
I2C-bus interface
PCF85xxC-2 family
11 I2C-BUS CHARACTERISTICS
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and
VIH with an input voltage swing from VSS to VDD; see Fig.10.
Note
1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be
internally provided by a transmitter.
SDA input/output (pin 5)
VIL
LOW level input voltage
0.8
0.3VDD
V
VIH
HIGH level input voltage
0.7VDD
+6.5
V
VOL
LOW level output voltage
IOL = 3 mA; VDD(min)
0.4
V
ILO
output leakage current
VOH =VDD
1
A
CI
input capacitance
VI =VSS
7pF
Data retention time
tS
data retention time
Tamb =55 °C10
years
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
fSCL
clock frequency
0
100
kHz
tBUF
bus free time between a STOP and START
condition
4.7
s
tHD;STA
START condition hold time after which rst clock
pulse is generated
4.0
s
tLOW
LOW level clock period
4.7
s
tHIGH
HIGH level clock period
4.0
s
tSU;STA
set-up time for STARt condition
repeated start
4.7
s
tHD;DAT
data hold time
for bus compatible masters
5
s
for bus devices
note 1
0
ns
tSU;DAT
data set-up time
250
ns
tr
SDA and SCL rise time
1
s
tf
SDA and SCL fall time
300
ns
tSU;STO
set-up time for STOP condition
4.0
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
相關(guān)PDF資料
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935182390112 1K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
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