參數(shù)資料
型號(hào)： 935185630112
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20
封裝： 0.300 INCH, PLASTIC, SOT-146-1, DIP-20
文件頁數(shù)： 9/12頁
文件大小： 104K
代理商： 935185630112
Philips Semiconductors
Product specification
74ABT273A
Octal D-type flip-flop
1995 Sep 06
6
AC SETUP REQUIREMENTS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Tamb = +25°C
VCC = +5.0V
Tamb = -40°C to +85°C
VCC = +5.0V ±0.5V
UNIT
Min
Typ
Min
ts(H)
ts(L)
Setup time, High or Low
Dn to CP
3
1.5
0.6
0.4
1.5
th(H)
th(L)
Hold time, High or Low
Dn to CP
3
0.7
-0.5
0.7
ns
tw(H)
tw(L)
Clock pulse width
High or Low
1
1.5
2.0
0.8
1.0
1.5
2.0
ns
tw(L)
Master Reset pulse width, Low
2
1.5
0.8
1.5
ns
tREC
Recovery time
MR to CP
2
1.5
0.5
1.5
ns
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
The shaded areas indicate when the input is permitted to change for predictable output performance.
VM
1/fMAX
tw(H)
tw(L)
tPHL
tPLH
CP
Qn
SA00056
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
VM
SF00158
MR
Qn
VM
tw(L)
tPHL
VM
tREC
CP
VM
Waveform 2. Master Reset Pulse Width, Master Reset to Output
Delay and Master Reset to Clock Recovery Time
th(H)
ts(H)
CP
SF00191
VM
th(L)
ts(L)
Dn
Waveform 3. Data Setup and Hold Times
相關(guān)PDF資料
PDF描述
935185610112 ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
935185650112 ABT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935185670112 ABT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935202220112 ABT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935185670118 ABT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
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