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參數(shù)資料
| 型號(hào)： | 935185650112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 鎖存器 |
| 英文描述： | ABT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-108-1, SO-14 |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大?。?/td> | 128K |
| 代理商： | 935185650112 |
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Philips Semiconductors
Product data
74ABT5074
Synchronizing dual D-type flip-flop
with metastable immune characteristics
2
2002 Dec 17
FEATURES
Metastable immune characteristics
Pin compatible with 74F74 and 74F5074
Typical f
MAX = 200 MHz
Output skew guaranteed less than 2.0 ns
High source current (I
OH = 15 mA) ideal for clock driver
applications
Output capability: +20 mA / –15 mA
Latch-up protection exceeds 50 0mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT5074 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set and reset inputs; also true and
complementary outputs.
Set (SDn) and reset (RDn) are asynchronous active-LOW inputs
and operate independently of the clock (CPn) input. Data must be
stable just one set-up time prior to the LOW-to-HIGH transition of
the clock for guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive-going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output.
The 74ABT5074 is designed so that the outputs can never display a
metastable state due to set-up and hold time violations. If set-up
time and hold time are violated the propagation delays may be
extended beyond the specifications, but the outputs will not glitch or
display a metastable state. Typical metastability parameters for the
74ABT5074 are:
τ 94 ps and To 1.3 × 107 sec
where
τ represents a function of the rate at which a latch in a
metastable state resolves that condition and T0 represents a
function of the measurement of the propensity of a latch to enter a
metastable state.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25 °C; GND = 0 V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
CPn to Qn or Qn
CL = 50 pF; VCC = 5 V
2.8
2.4
ns
CIN
Input capacitance
VI = 0 V or VCC
3
pF
ICC
Total supply current
Outputs disabled; VCC =5.5 V
2
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
PART NUMBER
DWG NUMBER
14-Pin plastic SO
–40
°C to +85 °C
74ABT5074D
SOT108-1
14-Pin Plastic SSOP Type II
–40
°C to +85 °C
74ABT5074DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40
°C to +85 °C
74ABT5074PW
SOT402-1
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
VCC
SD1
Q1
CP1
RD1
D1
RD0
D0
Q0
CP0
SD0
Q0
SA00001
PIN DESCRIPTION
PIN
SYMBOL
NAME AND FUNCTION
2, 12
D0, D1
Data inputs
3, 11
CP0, CP1
Clock inputs (active rising edge)
4, 10
SD0, SD1
Set inputs (active-LOW)
1, 13
RD0, RD1
Reset inputs (active-LOW)
5, 9
Q0, Q1
Data outputs (active-LOW), non-inverting
6, 8
Q0, Q1
Data outputs (active-LOW), inverting
7
GND
Ground (0 V)
14
VCC
Positive supply voltage
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