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參數(shù)資料
| 型號(hào)： | 935188340112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 173K |
| 代理商： | 935188340112 |
Philips Semiconductors - PIP - 74HC/HCT163; Presettable synchronous 4-bit binary counter; synchronous reset
Product Information
74HC/HCT163;
Presettable
synchronous 4-bit
binary counter;
synchronous reset
Information as of 2003-04-22
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Applications
Block diagram
topGeneral description
The 74HC/HCT163 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT163 are synchronous presettable binary counters which feature an internal look-ahead carry and can
be used for high-speed counting.
Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter
on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met).
Preset takes place regardless of the levels at count enable inputs (CEP and CET).
For the '163' the clear function is synchronous.
A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level after the
next positive-going transition on the clock (CP) input (provided that the set-up and hold time requirements for MR
are met). This action occurs regardless of the levels at PE, CET and CEP inputs.
This synchronous reset feature enables the designer to modify the maximum count with only one external NAND
gate.
The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be
HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled
will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be
used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74HC163N.html (1 of 5) [Apr-29-2003 12:17:47 PM]
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