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參數(shù)資料
| 型號： | 935189350118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 16 X 4 OTHER FIFO, 600 ns, PDSO16 |
| 封裝： | 5.30 MM, PLASTIC, MO-150AC, SOT-338-1, SSOP-16 |
| 文件頁數(shù)： | 17/25頁 |
| 文件大?。?/td> | 178K |
| 代理商： | 935189350118 |
24
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
7.1.2
ADC Noise Reduction Mode
When bits SM2:0 are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode,
stopping the CPU but allowing the ADC, the external interrupts, and the watchdog to continue operating (if
enabled). This sleep mode halts clk
I/O, clkCPU, and clkNVM, while allowing the other clocks to run.
This mode improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is
enabled, a conversion starts automatically when this mode is entered.
This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC.
7.1.3
Power-down Mode
When bits SM2:0 are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode,
the oscillator is stopped, while the external interrupts, and the watchdog continue operating (if enabled). Only a
watchdog reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep
mode halts all generated clocks, allowing operation of asynchronous modules only.
7.1.4
Standby Mode
When bits SM2:0 are written to 100, the SLEEP instruction makes the MCU enter Standby mode. This mode is
identical to Power-down with the exception that the oscillator is kept running. This reduces wake-up time, because
the oscillator is already running and doesn't need to be started up.
7.2
Power Reduction Register
The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 26, provides a method to
reduce power consumption by stopping the clock to individual peripherals. When the clock for a peripheral is
stopped then:
The current state of the peripheral is frozen.
The associated registers can not be read or written.
Resources used by the peripheral will remain occupied.
The peripheral should in most cases be disabled before stopping the clock. Clearing the PRR bit wakes up the
peripheral and puts it in the same state as before shutdown.
Peripheral shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consump-
tion. See “Supply Current of I/O Modules” on page 121 for examples. In all other sleep modes, the clock is already
stopped.
7.3
Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR Core controlled
system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so
that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In par-
ticular, the following modules may need special consideration when trying to achieve the lowest possible power
consumption.
7.3.1
Analog Comparator
When entering Idle mode, the analog comparator should be disabled if not used. In the power-down mode, the
analog comparator is automatically disabled. See “Analog Comparator” on page 80 for further details.
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