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參數(shù)資料
| 型號(hào)： | 935189710118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16 |
| 封裝： | SOT-338-1, SSOP-16 |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 152K |
| 代理商： | 935189710118 |
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Philips Semiconductors - PIP - 74HC/HCT173; Quad D-type flip-flop; positive-edge trigger; 3-state
Product Information
74HC/HCT173;
Quad D-type flip-
flop; positive-edge
trigger; 3-state
Information as of 2003-04-22
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Download datasheet
Applications
Block diagram
topGeneral description
The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (Q0 to Q3)
and master reset (MR).
When the two data enable inputs (E1 and E2) are LOW, the data on the Dn inputs is loaded into the register
synchronously with the LOW-to-HIGH clock (CP) transition. When one or both En inputs are HIGH one set-up time
prior to the LOW-to-HIGH clock transition, the register will retain the previous data. Data inputs and clock enable
inputs are fully edge-triggered and must be stable only one set-up time prior to the LOW-to-HIGH clock transition.
The master reset input (MR) is an active HIGH asynchronous input. When MR is HIGH, all four flip-flops are reset
(cleared) independently of any other input condition.
The 3-state output buffers are controlled by a 2-input NOR gate. When both output enable inputs (OE1 and OE2) are
LOW, the data in the register is presented to the Qn outputs. When one or both OEn inputs are HIGH, the outputs
are forced to a high impedance OFF-state. The 3-state output buffers are completely independent of the register
operation; the OEn transition does not affect the clock and reset operations.
topFeatures
q
Gated input enable for hold (do nothing) mode
q
Gated output enable control
q
Edge-triggered D-type register
q
Asynchronous master reset
q
Output capability: bus driver
q
ICC category: MSI
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74HC173N.html (1 of 4) [Apr-29-2003 12:25:31 PM]
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