參數(shù)資料
型號： 935190010112
廠商： NXP SEMICONDUCTORS
元件分類： 計數(shù)器
英文描述： HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED BIDIRECTIONAL DIVIDE BY N COUNTER, PDSO16
封裝： SOT-338-1, SSOP-16
文件頁數(shù)： 7/12頁
文件大小： 131K
代理商： 935190010112
1998 Jul 08
4
Philips Semiconductors
Product specication
Programmable divide-by-n counter
74HC/HCT4059
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay CP to Q
CL = 15 pF; VCC = 5 V 1820ns
fmax
maximum clock frequency
40
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per package
notes 1 and 2
30
32
pF
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
74HC4059N3;
74HCT4059N3
DIP24
plastic dual in-line package; 24 leads (300 mil)
SOT222-1
74HC4059N;
74HCT4059N
DIP24
plastic dual in-line package; 24 leads (600 mil)
SOT101-1
74HC4059D;
74HCT4059D
SO24
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
相關(guān)PDF資料
PDF描述
933757410118 HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED BIDIRECTIONAL DIVIDE BY N COUNTER, PDSO24
933757400112 HC/UH SERIES, ASYN POSITIVE EDGE TRIGGERED BIDIRECTIONAL DIVIDE BY N COUNTER, PDIP24
933757430118 HCT SERIES, ASYN POSITIVE EDGE TRIGGERED BIDIRECTIONAL DIVIDE BY N COUNTER, PDSO24
933835960005 HCT SERIES, ASYN POSITIVE EDGE TRIGGERED BIDIRECTIONAL DIVIDE BY N COUNTER, UUC
933757420112 HCT SERIES, ASYN POSITIVE EDGE TRIGGERED BIDIRECTIONAL DIVIDE BY N COUNTER, PDIP24
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