參數(shù)資料
型號(hào)： 935191070118
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 鎖存器
英文描述： LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
封裝： 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP1-16
文件頁(yè)數(shù)： 6/10頁(yè)
文件大?。?/td> 113K
代理商： 935191070118
Philips Semiconductors
Product specification
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
1998 Apr 28
5
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
°C to +85°C
UNIT
MIN
TYP1
MAX
V
HIGH level Input voltage
VCC = 1.2V
VCC
V
VIH
HIGH level Input voltage
VCC = 2.7 to 3.6V
2.0
V
LOW level Input voltage
VCC = 1.2V
GND
V
VIL
LOW level Input voltage
VCC = 2.7 to 3.6V
0.8
V
VCC = 2.7V; VI = VIH or VIL; IO = –12mA
VCC*0.5
VO
HIGH level output voltage
VCC = 3.0V; VI = VIH or VIL; IO = –100A
VCC*0.2
VCC
V
VOH
HIGH level output voltage
VCC = 3.0V; VI = VIH or VIL; IO = –12mA
VCC*0.6
V
VCC = 3.0V; VI = VIH or VIL; IO = –24mA
VCC*1.0
VCC = 2.7V; VI = VIH or VIL; IO = 12mA
0.40
VOL
LOW level output voltage
VCC = 3.0V; VI = VIH or VIL; IO = 100A
GND
0.20
V
VCC = 3.0V; VI = VIH or VIL; IO = 24mA
0.55
I
Input leakage current
VCC =3 6V; V = 5 5V or GND
"01
"5
A
II
Input leakage current
VCC = 3.6V; VI = 5.5V or GND
"0.1
"5
A
ICC
Quiescent supply current
VCC = 3.6V; VI = VCC or GND; IO = 0
0.1
10
A
ICC
Additional quiescent supply current per
input pin
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0
5
500
A
NOTE:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500W; Tamb = –40_C to +85_C
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3V ±0.3V
VCC = 2.7V
UNIT
MIN
TYP1
MAX
MIN
TYP
NO TAG
MAX
tPHL/tPLH
Propagation delay
nCP to nQ, nQ
Figures 1, 3
4.3
7.5
8.5
ns
tPLH
Propagation delay
nSD to nQ
nRD to nQ
Figures 2, 3
4.5
8.0
9.0
ns
tPHL
Propagation delay
nSD to nQ
nRD to nQ
Figures 2, 3
5.2
9.0
10
ns
tW
Clock pulse width
HIGH or LOW
Figure 1
3.3
2.0
ns
tW
Set or reset pulse width
HIGH or LOW
Figure 2
3.0
ns
trem
Removal time
nSD, nRD to nCP
Figure 2
3.0
ns
tsu
Set-up time
nJ, nK to CP
Figure 1
2.5
ns
th
Hold time
nJ, nK to nCP
Figure 1
2.0
ns
fmax
Maximum clock pulse
frequency
Figure 1
150
225
MHz
NOTE:
1. These typical values are at VCC = 3.3V and Tamb = 25°C.
相關(guān)PDF資料
PDF描述
0676.050 CONNECTOR ACCESSORY
935191100112 ALVC/VCX/A SERIES, 16 1-BIT DRIVER, INVERTED OUTPUT, PDSO48
935191100118 ALVC/VCX/A SERIES, 16 1-BIT DRIVER, INVERTED OUTPUT, PDSO48
935210850112 ALVC/VCX/A SERIES, 16 1-BIT DRIVER, INVERTED OUTPUT, PDSO48
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