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參數(shù)資料
| 型號： | 935191100118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 16 1-BIT DRIVER, INVERTED OUTPUT, PDSO48 |
| 封裝： | 7.50 MM, PLASTIC, MO-118AA, SOT-370-1, SSOP3-48 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 107K |
| 代理商： | 935191100118 |
Philips Semiconductors
Product specification
74ALVCH16540
16-bit buffer/line driver, inverting,
5V input tolerant (3-State)
2
1997 Aug 11
853-2020 18266
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple V
CC and ground pins for minimum noise
and ground bounce
Direct interface with TTL levels
Bus hold on all data inputs eliminates the need for external pull-up
resistors to hold unused inputs
Output drive capability 50 transmission lines @ 85°C
DESCRIPTION
The 74ALVCH16540 is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74ALVCH16540 is a 16-bit inverting buffer/line driver with
3-State outputs. The 3-State outputs are controlled by the output
enable inputs 1OEn and 2OEn. A HIGH on nOEn causes the outputs
to assume a high impedance OFF-state.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level. This feature eliminates the need for
external pull-up or pull-down resistors. The device can be used as
four 4-bit buffers, two 8-bit buffers or one 16-bit buffer.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1OE1
1Y0
1Y1
GND
1Y2
1Y3
VCC
1Y5
GND
1Y6
1Y7
2Y0
2Y1
GND
1Y4
2Y2
2Y3
VCC
2Y4
2Y5
2A5
2A4
VCC
2A3
2A2
GND
2A1
2A0
1A7
1A6
GND
1A5
1A4
VCC
1A3
1A2
GND
1A1
1A0
1OE2
21
22
23
24
25
26
27
28
GND
2Y6
2Y7
2OE1
2OE2
2A7
2A6
GND
SW00108
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
/t
Propagation delay
1An to 1Yn;
CL = 50pF
VCC = 3.3V
1.8
ns
tPHL/tPLH
1An to 1Yn;
2An to 2Yn
CL = 30pF
VCC = 2.5V
1.8
ns
CI
Input capacitance
5.0
pF
C
Power dissipation capacitance per buffer
V = GND to VCC1
Outputs enabled
26
pF
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
Outputs disabled
5
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
48-Pin Plastic SSOP Type III
–40
°C to +85°C
74ALVCH16540 DL
ACH16540 DL
SOT370-1
48-Pin Plastic TSSOP Type II
–40
°C to +85°C
74ALVCH16540 DGG
ACH16540 DGG
SOT362-1
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