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參數(shù)資料
| 型號(hào)： | 935192230015 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | REAL TIME CLOCK, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 4/31頁 |
| 文件大?。?/td> | 213K |
| 代理商： | 935192230015 |
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1997 Mar 25
12
Philips Semiconductors
Product specication
Low power clock/calendar
PCF8593
Fig.10 Alarm control register, event-counter mode.
handbook, full pagewidth
memory location 08
timer function :
000
no timer
001
units
010
100
011
10 000
100
1 000 000
101
not allowed
110
not allowed
111
test mode, all counters
in parallel
timer interrupt enable :
0
timer flag, no interrupt
1
timer flag, interrupt
clock alarm function :
00
no event alarm
01
event alarm
10
not allowed
11not allowed
timer alarm enable :
0
no timer alarm
1
timer alarm
alarm interrupt enable :
0
alarm flag, no interrupt
1
alarm flag, interrupt
7
654
321
0
MSB
LSB
MBD817
7.9
Interrupt output
The conditions for activating the open-drain n-channel
interrupt output INT (active LOW) are determined by
appropriate programming of the alarm control register.
These conditions are clock alarm, timer alarm, timer
overflow, and event counter alarm. An interrupt occurs
when the alarm flag or the timer flag is set, and the
corresponding interrupt is enabled. In all events, the
interrupt is cleared only by software resetting of the flag
which initiated the interrupt.
In the clock mode, if the alarm enable is not activated
(alarm enable bit of control/status register is logic 0), the
interrupt output toggles at 1 Hz with a 50% duty cycle (may
be used for calibration). The OFF voltage of the interrupt
output may exceed the supply voltage, up to a maximum
of 6.0 V. A logic diagram of the interrupt output is shown in
Fig.11.
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