參數(shù)資料
型號： 935195460112
廠商： NXP SEMICONDUCTORS
元件分類： 總線收發(fā)器
英文描述： ABT SERIES, 16 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封裝： 7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP3-56
文件頁數(shù)： 7/12頁
文件大?。?/td> 113K
代理商： 935195460112
Philips Semiconductors
Product data
74ABT16652
16-bit transceiver/register, non-inverting (3-State)
2002 Apr 03
4
LOGIC DIAGRAM
1D
C1
Q
DETAIL A X 7
nB0
1D
C1
Q
nA0
1of 8 Channels
nA7
nA6
nA5
nA4
nA3
nA2
nA1
nB1
nB2
nB3
nB4
nB5
nB6
nB7
nOEBA
nOEAB
nCPBA
nSBA
nCPAB
nSAB
SH00065
FUNCTION TABLE
INPUTS
DATA I/O
OPERATING MODE
nOEAB
nOEBA
nCPAB
nCPBA
nSAB
nSBA
nAx
nBx
L
H
H or L
↑
H or L
↑
X
Input
Isolation
Store A and B data
X
H
↑
H or L
↑
X
**
X
Input
Unspecified
output*
Store A, Hold B
Store A in both registers
L
X
L
H or L
↑
X
**
Unspecified
output*
Input
Hold A, Store B
Store B in both registers
L
X
H or L
X
L
H
Output
Input
Real time B data to A bus
Stored B data to A bus
H
X
H or L
X
L
H
X
Input
Output
Real time A data to B bus
Store A data to B bus
H
L
H or L
H
Output
Stored A data to B bus
Stored B data to A bus
H = HIGH voltage level
L
= LOW voltage level
X = Don’t care
↑ = Low-to-High clock transition
*
The data output function may be enabled or disabled by various signals at the nOEBA and nOEAB inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.
**
If both Select controls (nSAB and nSBA) are LOW, then clocks can occur simultaneously. If either Select control is HIGH, the clocks must
be staggered in order to load both registers.
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