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參數(shù)資料
| 型號： | 935196500112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 6/35頁 |
| 文件大?。?/td> | 243K |
| 代理商： | 935196500112 |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁
1997 Apr 16
14
Philips Semiconductors
Product specication
8-bit microcontrollers with DTMF generator,
8 kbytes OTP and 128 bytes EEPROM
PCD3755A; PCD3755E;
PCD3755F
7.1.2
EEPROM ADDRESS REGISTER (ADDR)
The EEPROM Address Register determines the EEPROM location to which an EEPROM access is directed.
As a whole, ADDR auto-increments after read and write cycles to EEPROM, but remains xed after erase cycles. This
behaviour generates the correct ADDR contents for sequential read accesses and for sequential write or erase/write
accesses with intermediate page setup. Overow of the 8-bit counter wraps around to zero.
Table 13 EEPROM Address Register (address 01H, access type R/W)
Table 14 Description of ADDR bits
7.1.3
EEPROM DATA REGISTER (DATR)
Table 15 EEPROM Data Register (address 03H; access type R/W)
Table 16 Description of DATR bits
7.1.4
EEPROM TEST REGISTER (TST)
The EEPROM Test register is used for testing purposes during device manufacture. It must not be accessed by the
device user.
76543210
0
AD6
AD5
AD4
AD3
AD2
AD1
AD0
BIT
MNEMONIC
DESCRIPTION
7
This bit is set to a logic 0.
6 to 2
AD6 to AD2
AD2 to AD6 select one of 32 pages.
1 to 0
AD1 to AD0
AD1 and AD0 are irrelevant during erase and write cycles. For read accesses, AD0 and
AD1 indicate the byte location within an EEPROM page. During page setup, finally, AD0
and AD1 select EEPROM Latch 0 to 3 whereas AD2 to AD6 are irrelevant. If increment
mode (Table 12) is active during page setup, the subcounter consisting of AD0 and AD1
increments after every write to an EEPROM latch, thus enhancing access to sequential
EEPROM latches. Incrementing stops when EEPROM Latch 3 is reached, i.e. when
AD0 and AD1 are both a logic 1.
76543210
D7
D6
D5
D4
D3
D2
D1
D0
BIT
MNEMONIC
DESCRIPTION
7 to 0
D7 to D0
The EEPROM Data Register (DATR) is only a conceptual entity. A read operation from
DATR, reads out the EEPROM byte addressed by ADDR. On the other hand, a write
operation to DATR, loads data into the EEPROM latch (see Fig.5) defined by bits AD0
and AD1 of ADDR.
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