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參數(shù)資料
| 型號(hào)： | 935196750118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ABT SERIES, 18 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP3-56 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大小： | 104K |
| 代理商： | 935196750118 |
Philips Semiconductors
Product data
74ABT16501A
18-bit universal bus transceiver (3-State)
2
2002 Apr 03
853-1788 27958
FEATURES
18-bit bidirectional bus interface
3-State buffers
Output capability: +64 mA/–32 mA
TTL input and output switching levels
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
Positive edge-triggered clock inputs
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Flexible operation permits 18 embedded D-type latches or
flip-flops to operate in clocked, transparent, and latched modes.
DESCRIPTION
The 74ABT16501A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA)
inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is latched
if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the
A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH
transition of CPAB. When OEAB is HIGH, the outputs are active.
When OEAB is LOW, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA. The output enables are complimentary (OEAB is
Active-HIGH, and OEBA is Active-LOW).
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25 °C; GND = 0 V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50 pF;
VCC = 5 V
2.2
1.8
ns
CIN
Input capacitance (Control pins)
VI = 0 V or VCC
3
pF
CI/O
I/O pin capacitance
Outputs disabled; VI/O = 0 V or VCC
7
pF
ICCZ
Quiescent supply current
Outputs disabled; VCC = 5.5 V
500
A
ICCL
Quiescent supply current
Outputs LOW; VCC = 5.5 V
9
mA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°C to +85 °C
74ABT16501ADL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°C to +85 °C
74ABT16501ADGG
SOT364-1
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