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參數(shù)資料
| 型號： | 935197100112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | F/FAST SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, SOT-38-4, DIP-16 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 79K |
| 代理商： | 935197100112 |
Philips Semiconductors
Product specification
74F257A
Quad 2-line to 1-line selector/multiplexer, non-inverting
(3-State)
2
1995 Mar 31
853–0360 15059
FEATURES
Industrial range available (–40°C to +85°C)
Multifunction capability
Non-inverting data path
3-State outputs
See 74F258A for inverting version
DESCRIPTION
The 74F257A has four identical 2-input multiplexers with 3-State
outputs which select 4 bits of data from two sources uncer control of
a common Select (S) input. The I0a inputs are selected when the
common Select input is Low and the I1n inputs are selected when
the common Select input is High. Data appears at the outputs in true
non-inverted form from the selected inputs. The 74F257A is the logic
implementation of a 4-pole, 2-position switch where the position of
the switch is determined by the logic levels supplied to the common
Slect input. Outputs are forced to a high impedance “off” state when
the Output Enable (OE) is High. All but one device must be in high
impedance state to avoid currents that would exceed the maximum
rating if the outputs were tied together. Design of the Output Enable
signals must ensure that there is no overlap when outputs of 3-state
devices were tied together.
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
Yb
VCC
Yd
I0c
I1c
I1d
OE
I0d
S
I0a
I1b
I1a
Ya
I0b
9
8
GND
Yc
SF00673
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F257A
4.3ns
12mA
ORDERING INFORMATION
ORDER CODE
DRAWING
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
INDUSTRIAL RANGE
VCC = 5V ±10%, Tamb = –40°C to +85°C
DRAWING
NUMBER
16-pin plastic DIP
N74F257AN
I74F257AN
SOT38-4
16-pin plastic SO
N74F257AD
I74F257AD
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
I0n, I1n
Data inputs
1.0/1.0
20
A/0.6mA
S
Common Select input
1.0/1.0
20
A/0.6mA
OE
Output Enable input (active Low)
1.0/1.0
20
A/0.6mA
Ya – Yd
Data outputs
150/33
3.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20
A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
VCC = Pin 16
GND = Pin 8
SF00674
1
15
S
OE
2356
11
10
14
I0a
I1a
I0b
I1b
I0c
I1c
I0d
Ya
Yb
Yc
Yd
479
12
13
I1d
LOGIC SYMBOL (IEEE/IEC)
SF00675
2
1
15
EN
1
G1
3
4
1
MUX
5
6
7
10
11
9
13
14
12
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