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參數(shù)資料
| 型號： | 935201030118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, SOT-96-1, SO-8 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 208K |
| 代理商： | 935201030118 |
Philips Semiconductors
Product specification
SA5223
Wide dynamic range AGC transimpedance amplifier(150MHz)
1995 Oct 24
3
DC ELECTRICAL CHARACTERISTICS
Typical data and Min and Max limits apply at TA = 25°C, and VCC = +5V, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
SA5223
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
VIN
Input bias voltage
1.3
1.55
1.8
V
VO±
Output bias voltage
2.9
3.2
3.5
V
VOS
Output offset voltage (VPIN6 - VPIN7)
-200
80
+200
mV
ICC
Supply current
15
22
29
mA
IOMAX
Output sink/source current
1.5
2
mA
NOTE: Standard deviations are estimated from design simulations to represent manufacturing variations over the life of the product.
AC ELECTRICAL CHARACTERISTICS
Typical data and Min and Max limits apply at TA = 25°C and VCC = +5V, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
SA5223
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
RT
Transresistance (differential output)
DC tested, RL = ∞, IIN = 0-1A
90
125
160
k
RT
Transresistance
(single-ended output)
DC tested, RL = ∞, IIN = 0-1A
45
62.5
80
k
RO
Output resistance
(differential output)
DC tested
140
RO
Output resistance
(single-ended output)
DC tested
70
f3dB
Bandwidth (-3dB)
Test Circuit 1
110
150
MHz
RIN
Input resistance
DC tested
250
CIN
Input capacitance1
0.7
pF
CINT
Input capacitance including Miller multiplied
capacitance
4.0
pF
R/V
Transresistance power supply sensitivity
VCC1 = VCC2 = 5 ±0.5V
3
%/V
R/T
Transresistance ambient temperature sensi-
tivity
TA = TA MAX - TA MIN
0.09
%/oC
IIN
RMS noise current spectral density (referred
to input)2
Test Circuit 2, f = 10MHz
1.17
pA
Hz
Integrated RMS noise current over the band-
idth (referred to inp t)
Test circuit 2,
f = 50MHz
7
width (referred to input)
CS = 0.1pF
f = 100MHz
12
IT
CS = 0.1F
f = 150MHz
16
nA
T
f = 50MHz
8
CS = 0.4pF
f = 100MHz
13
f = 150MHz
18
PSRR
Power supply rejection ratio (change in VOS)
DC Tested,
VCC = ±0.5V
–55
dB
PSRR
Power supply rejection ratio3
f = 1.0MHz, Test Circuit 3
–20
dB
VOLMAX
Maximum differential output AC voltage
Ii = 0–2mA peak AC
800
mV
dR
T
dt
AGC loop time constant parameter4
10
A to 20A steps
1
dB/ms
IINMAX
Maximum input amplitude for output duty
cycle of 50
±5%
Test circuit 4
+2
mA
tr, tf
Output rise and fall times
10 – 90%
2.2
ns
tD
Group delay
f = 10MHz
2.2
ns
NOTES:
1. Does not include Miller-multiplied capacitance of input device.
2. Noise performance measured differential. Single-ended output noise is higher due to CM noise.
3. PSRR is output referenced and is circuit board layout dependent at higher frequencies. For best performance use a RF filter in VCC line.
4. This implies that the SA5223 gain will change 1dB (10%) in the absence of data for 1ms (i.e., can handle bursty data without degrading Bit
Error Rate (BER) for 100,000 cycles at 100MHz).
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