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參數(shù)資料
| 型號： | 935203010118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 120K |
| 代理商： | 935203010118 |
Philips Semiconductors
Product data
74LVT16374A
3.3V 16-bit edge-triggered D-type flip-flop
(3-State)
2002 Nov 01
4
PIN DESCRIPTION (SSOP AND TSSOP PACKAGE
OPTIONS)
PIN NUMBER
SYMBOL
FUNCTION
47, 46, 44, 43, 41, 40,
38, 37 36, 35, 33, 32,
30, 29, 27, 26
1D0 - 1D7
2D0 - 2D7
Data inputs
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20,
22, 23
1Q0 - 1Q7
2Q0 - 2Q7
Data outputs
1, 24
1OE, 2OE
Output enable inputs
(active-Low)
48, 25
1CP, 2CP
Clock pulse inputs (active
rising edge)
4, 10, 15, 21, 28, 34,
39, 45
GND
Ground (0 V)
7, 18, 31, 42
VCC
Positive supply voltage
EV PACKAGE TERMINAL PLACEMENT, TOP VIEW
SR0243
123
456
A
B
C
D
G
H
J
K
E
F
TERMINAL ASSIGNMENTS FOR 74LVT16374A IN VFBGA
1
2
3
4
5
6
A
1 OEn
NC
1CP
B
1Q1
1Q0
GND
1D0
1D1
C
1Q3
1Q2
Vcc
1D2
1D3
D
1Q5
1Q4
GND
1D4
1D5
E
1Q7
1Q6
1D6
1D7
F
2Q0
2Q1
2D1
2D0
G
2Q2
2Q3
GND
2D3
2D2
H
2Q4
2Q5
Vcc
2D5
2D4
J
2Q6
2Q7
GND
2D7
2D6
K
2OEn
NC
2CP
NOTE:
1. “n” is used to indicate active low in these tables but use standard method in the data sheets
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUTS
OPERATING MODE
nOE
nCP
nDx
REGISTER
nQ0 - nQ7
OPERATING MODE
L
↑
l
h
L
H
L
H
Load and read register
L
↑
X
NC
Hold
H
↑
X
nDx
NC
nDx
Z
Disable outputs
H = High voltage level
h
= High voltage level one set-up time prior to the High-to-Low E transition
L
= Low voltage level
l
= Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-High clock transition
↑ = Not a Low-to-High clock transition
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