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參數(shù)資料
| 型號(hào)： | 935203320112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 鎖存器 |
| 英文描述： | ABT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153ED, SOT-362-1, TSSOP-48 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 95K |
| 代理商： | 935203320112 |
Philips Semiconductors
Product specification
74ABT16273
74ABTH16273
16-bit D-type flip-flop
1998 Feb 27
3
LOGIC SYMBOL (IEEE/IEC)
1
1D
2
2D
SH00053
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
R1
C1
R2
C2
1MR
1Q0
!Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q3
2Q4
2Q2
2Q5
2Q7
2MR
2Q6
CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D3
2D4
2D2
2D5
2D7
2CP
2D6
FUNCTION TABLE
Inputs
Output
operating
mode
nMR
nCP
nDX
nQ0-nQ7
mode
L
X
L
Reset (clear)
H
↑
h
H
Load “1”
H
↑
I
L
Load “0”
H
L
X
Q0
Retain state
H = High voltage level
h
= high voltage level one set-up time prior to the Low-to-High
clock transition
L
= Low voltage level
I
= Low voltage level one set-up time prior to the Low-to-High
clock transition
X = Don’t care
↑ = Low-to-High clock transition
Q0=
Output as it was
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1MR
1Q0
!Q1
GND
1Q2
1Q3
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q3
VCC
2Q4
VCC
2Q2
2Q5
GND
2Q7
2MR
2Q6
CP
1D0
1D1
GND
1D2
1D3
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D3
VCC
2D4
VCC
2D2
2D5
GND
2D7
2CP
2D6
SH00054
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