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參數(shù)資料
| 型號： | 935207360118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | ABT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 |
| 封裝： | 7.50 MM, PLASTIC, MO-118AA, SOT-370-1, SSOP-48 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 95K |
| 代理商： | 935207360118 |
Philips Semiconductors
Product specification
74ABT16273
74ABTH16273
16-bit D-type flip-flop
1998 Feb 27
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = +25
°C
Temp = -40
°C
to +85
°C
UNIT
MIN
TYP
MAX
MIN
MAX
VIK
Input clamp voltage
VCC = 4.5V; IIK = –18mA
0.9
–1.2
V
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
2.5
2.9
2.5
VOH
High-level output voltage
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
3.0
3.4
3.0
V
VCC = 4.5V; IOH = –32mA; VIL or VIH
2.0
2.4
2.0
VOL
Low-level output voltage
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
0.42
0.55
VRST
Power-up output
voltage3
VCC = 5.5V; IO = 1mA; VI = GND or VCC
0.13
0.55
V
Input leakage current
I
Input leakage current
VCC =5 5V; V =VCC or GND
±01
±1
A
II
g
74ABT16273
VCC = 5.5V; VI = VCC or GND
±0.1
±1
A
I
74ABT16273
CC
I
CC
Input leakage current
VCC = 5.5V; VI = VCC or GND
Control
pins
±0.01
±1
A
II
In ut leakage current
74ABTH16273
VCC = 5.5V; VI = VCC
Data pins
0.01
1
A
VCC = 5.5V; VI = 0
Data pins
–2
–3
–5
A
B
H ld
t i
t 4
VCC = 4.5V; VI = 0.8V
35
IHOLD
Bus Hold current inputs4
74ABTH16273
VCC = 4.5V; VI = 2.0V
–75
A
VCC = 5.5V; VI = 0 to 5.5V
±800
IOFF
Power-off leakage
current
VCC= 0.0V; VO or VI t 4.5V
±5.0
±100
A
IO
output current1
VCC = 5.5V; VO = 2.5V
–50
–70
–180
–50
–180
mA
ICEX
Output High leakage
current
VCC = 5.5V; VO = 5.5V; VI = GND or VCC
5.0
50
A
ICCH
Quiescent supply current
VCC = 5.5V; Outputs High, VI = GND or VCC
0.2
1
mA
ICCL
Quiescent supply current
VCC = 5.5V; Outputs Low, VI = GND or VCC
8
19
mA
ICC
Additional supply current
per input pin2
74ABT16273
VCC = 5.5V; One input at 3.4V.
Other inputs at VCC or GND
5
100
A
ICC
Additional supply current
per input pin2
74ABTH16273
VCC = 5.5V; One input at 3.4V.
Other inputs at VCC or GND
0.2
1
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500;
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Tamb = +25°C
VCC = +5.0V
Tamb = –40 to +85 °C
VCC = +5.0V ±0.5V
UNIT
MIN
TYP
MAX
MIN
MAX
tPLH
tPHL
Propagation delay
nCP to nQx
1
1.5
1.2
2.5
2.0
3.4
2.7
1.5
1.2
4.0
3.0
ns
tPHL
Propagation delay
nMR to nQx
2
1.9
3.7
4.3
1.9
5.3
ns
fMAX
Maximum clock frequency
1
150
240
150
MHz
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