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參數(shù)資料
| 型號： | 935208550112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 4/80頁 |
| 文件大?。?/td> | 446K |
| 代理商： | 935208550112 |
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1997 Dec 15
12
Philips Semiconductors
Product specication
8-bit microcontrollers
P83C524; P80C528; P83C528
Note
1. To avoid a 'latch-up' effect at power-on, the voltage on any pin (at any time) must not be higher than VDD +0.5 V or
lower than VSS 0.5 V respectively.
XTAL1
19
21
15
Crystal input 1: input to the inverting amplier that forms the
oscillator, and input to the internal clock generator. Receives the
external oscillator clock signal when an external oscillator is used
(see Figures 22 and 23).
VSS
20
22
16
Ground: circuit ground potential.
P2.0-P2.7
21
28
24
31
(23 n.c.)
18
25
(17 n.c.)
Port 2: 8-bit quasi-bidirectional I/O Port with internal pull-ups.
During access to external memories (RAM/ROM) that use 16-bit
addresses (MOVX @DPTR) Port 2 emits the high-order address
byte (A8 to A15). Port 2 can sink/source one TTL (= 4 LSTTL)
input. It can drive CMOS inputs without external pull-ups.
PSEN
29
32
26
Program Store Enable output: read strobe to the external
program memory via Port 0 and Port 2. It is activated twice each
machine cycle during fetches from external program memory.
When executing out of external program memory two activations of
PSEN are skipped during each access to external data memory.
PSEN is not activated (remains HIGH) during no fetches from
external program memory. PSEN can sink/source 8 LSTTL inputs.
It can drive CMOS inputs without external pull-ups.
ALE
30
33
27
Address Latch Enable output: latches the LOW byte of the
address during access to external memory in normal operation. It
is activated every six oscillator periods except during an external
data memory access. ALE can sink/source 8 LSTTL inputs. It can
drive CMOS inputs without an external pull-up.
EA
31
35
(34 n.c.)
29
(28 n.c.)
External Access input: when during RESET, EA is held at a TTL
HIGH level, the CPU executes out of the internal program ROM,
provided the program counter is less than 32768. When EA is held
at a TTL LOW level during RESET, the CPU executes out of
external program memory via Port 0 and Port 2. EA is not allowed
to oat.
P0.0-P0.7
32
39
36
43
30
37
Port 0: 8-bit open drain bidirectional I/O Port. It is also the
multiplexed low-order address and data bus during accesses to
external memory (AD0 to AD7). During these accesses internal
pull-ups are activated. Port 0 can sink/source 8 LSTTL inputs.
VDD
40
44
38
Power supply: +5 V power supply pin during normal operation,
Idle mode and Power-down mode.
SYMBOL
PIN
DESCRIPTION
SOT 129-1 SOT 187-2 SOT 307-2
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