參數(shù)資料
型號： 935208750112
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： ABT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝： PLASTIC, SOT-337-1, SSOP2-14
文件頁數(shù)： 3/5頁
文件大小： 65K
代理商： 935208750112
Philips Semiconductors
Product specification
74ABT74
Dual D-type flip-flop
1995 Sep 22
3
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = +25°C
Tamb = –40°C
to +85
°C
UNIT
MIN
TYP
MAX
MIN
MAX
VIK
Input clamp voltage
VCC = 4.5V; IIK = –18mA
–0.9
–1.2
V
VOH
High-level output voltage
VCC = 4.5V; IOH = –15mA; VI = VIL or VIH
2.5
2.9
2.5
V
VOL
Low-level output voltage
VCC = 4.5V; IOL = 20mA; VI = VIL or VIH
0.35
0.5
V
II
Input leakage current
VCC = 5.5V; VI = GND or 5.5V
±0.01
±1.0
A
IOFF
Power-off leakage current
VCC = 0.0V; VO or VI ≤ 4.5V
±5.0
±100
A
ICEX
Output High leakage current
VCC = 5.5V; VO = 5.5V; VI = GND or VCC
5.0
50
A
IO
Output current1
VCC = 5.5V; VO = 2.5V
–50
–75
–180
–50
–180
mA
ICC
Quiescent supply current
VCC = 5.5V; VI = GND or VCC
2
50
A
ICC
Additional supply current per
input pin2
VCC = 5.5V; One data input at 3.4V, other
inputs at VCC or GND
0.25
500
A
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flop or latch after applying the power.
AC ELECTRICAL CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500
SYMBOL
PARAMETER
WAVEFORM
LIMITS
UNIT
SYMBOL
PARAMETER
WAVEFORM
Tamb = +25°C
VCC = +5.0V
Tamb = –40°C to +85°C
VCC = +5.0V ±0.5V
UNIT
MIN
TYP
MAX
MIN
MAX
fMAX
Maximum clock frequency
1
180
250
150
MHz
tPLH
tPHL
Propagation delay
CPn to Qn, Qn
1
1.0
3.0
2.5
4.2
3.5
1.0
4.7
4.0
ns
tPLH
tPHL
Propagation delay
Sn, Rn to Qn, Qn
3
1.0
3.4
2.9
4.9
4.5
1.0
6.2
5.2
ns
tOSHL
tOSLH1
Output to Output skew
An or Bn to Yn
4
0.5
0.6
ns
NOTE:
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same
device. The specification applies to any outputs switching in the the same direction, either HIGH–to-LOW (tOSHL) or LOW-to-HIGH (tOSLH);
parameter guaranteed by design.
AC SETUP REQUIREMENTS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500
SYMBOL
PARAMETER
WAVEFORM
LIMITS
UNIT
SYMBOL
PARAMETER
WAVEFORM
Tamb = +25°C
VCC = +5.0V
Tamb = –40°C to +85°C
VCC = +5.0V ±0.5V
UNIT
MIN
TYP
MIN
tsu (H)
tsu (L)
Setup time, high or low
Dn to CPn
1
2.6
2.4
1.4
2.6
2.4
ns
th (H)
th (L)
Hold time, high or low
Dn to CPn
1
0
–1.4
0
ns
tw (H)
tw (L)
CPn pulse width,
high or low
1
1.7
1.0
2.1
ns
tw (L)
SDn, RDn pulse width, low
3
2.0
1.3
2.2
ns
trec
Recovery time
SDn, RDn to CPn
2
2.1
1.4
2.4
ns
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