參數(shù)資料
型號(hào)： 935209250118
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： LVT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝： 3.90 MM, PLASTIC, MS-012AB, SOT-108-1, SO-14
文件頁(yè)數(shù)： 6/13頁(yè)
文件大小： 175K
代理商： 935209250118
Philips Semiconductors
Product specification
74LVT74
3.3V Dual D-type flip-flop
2
1996 Aug 28
853-1872 17244
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25°C;
GND = 0V
TYPICAL
UNIT
tPLH
tPHL
Propagation
delay
CPn to Qn
CL = 50pF;
VCC = 3.3V
3.1
3.6
ns
CIN
Input
capacitance
VI = 0V or 3.0V
3
pF
ICC
Total supply
current
VCC = 3.6V
0.5
mA
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
VCC
SD1
Q1
CP1
RD1
D1
RD0
D0
Q0
CP0
SD0
Q0
SF00045
LOGIC SYMBOL
Q0 Q0Q1 Q1
56
98
VCC = Pin 14
GND = Pin 7
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
D0
D1
212
SA00359
DESCRIPTION
The 74LVT74 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock input.
When set and reset are inactive (high), data at the D input is
transferred to the Q and Q outputs on the low-to-high transition of
the clock. Data must be stable just one setup time prior to the
low-to-high transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. Following the hold time
interval, data at the D input may be changed without affecting the
levels of the output.
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
2, 12
D0, D1
Data inputs
3, 11
CP0, CP1
Clock inputs (active rising edge)
4, 10
SD0, SD1
Set inputs (active LOW)
1, 13
RD0, RD1
Reset inputs (active LOW)
5, 6, 8, 9
Qn, Qn
Data outputs
LOGIC SYMBOL (IEEE/IEC)
4
3
2
1
10
11
12
13
5
6
9
8
&
S
C1
C2
R
1D
2D
R
SF00047
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
14-Pin Plastic SO
–40
°C to +85°C
74LVT74 D
SOT108-1
14-Pin Plastic SSOP
–40
°C to +85°C
74LVT74 DB
SOT337-1
14-Pin Plastic TSSOP
–40
°C to +85°C
74LVT74 PW
74LVT74PW DH
SOT402-1
相關(guān)PDF資料
PDF描述
935209260118 LVT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935209250112 LVT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935209290112 LVT SERIES, QUAD 2-INPUT XOR GATE, PDSO14
935209300112 LVT SERIES, QUAD 2-INPUT XOR GATE, PDSO14
935209280112 LVT SERIES, QUAD 2-INPUT XOR GATE, PDSO14
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