參數(shù)資料
型號(hào)： 935209270118
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： LVT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝： 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14
文件頁(yè)數(shù)： 3/13頁(yè)
文件大小： 175K
代理商： 935209270118
Philips Semiconductors - PIP - 74LVT74; 3.3V Dual D-type flip-flop
Product Information
74LVT74; 3.3V Dual
D-type flip-flop
Information as of 2003-04-22
Stay informed
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Features
topGeneral description
The 74LVT74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset
inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and
operate independently of the clock input. When set and reset are inactive (high), data at the D input is
transferred to the Q and Q outputs on the low-to-high transition of the clock. Data must be stable just one setup
time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a
voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold
time interval, data at the D input may be changed without affecting the levels of the output.
topApplications
topDatasheet
Page
count
File size
(kB)
Datasheet
74LVT74
3.3V
Dual D-
type flip-
flop
8/28/1996
Product specification 4
97
topBlockdiagram(s)
Block diagram of
74LVT74D
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74LVT74D.html (1 of 3) [May-09-2003 6:10:36 PM]
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相關(guān)PDF資料
PDF描述
935209250118 LVT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935209260118 LVT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935209250112 LVT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935209290112 LVT SERIES, QUAD 2-INPUT XOR GATE, PDSO14
935209300112 LVT SERIES, QUAD 2-INPUT XOR GATE, PDSO14
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