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參數(shù)資料
| 型號： | 935223090112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | Buffer和線驅(qū)動 |
| 英文描述： | OCTAL LINE TRANSCEIVER, PDSO48 |
| 封裝： | PLASTIC, SSOP2-48 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 159K |
| 代理商： | 935223090112 |
Philips Semiconductors
Product specification
PDI1284P11
3.3V Parallel interface transceiver/buffer
1999 Sep 17
7
AC CHARACTERISTICS
GND = 0V, tR = tF = 3.0ns, CL = 50pF, RL = 500
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
WAVEFORMS
Tamb = 0°C to +70°C
UNIT
MIN
TYP
MAX
tpLH
Propagation delay
PathAtoBorY
25
0
20
ns
tpHL
Propagation delay
Path A to B or Y
2, 5
0
20
ns
tpLH
Propagation delay
PathBtoA
25
0
12
ns
tpHL
Propagation delay
Path B to A
2, 5
0
12
ns
tpLH
Propagation delay
PathCtoA
25
15
ns
tpHL
Propagation delay
Path C to A
2, 5
15
ns
tpLH
Propagation delay
Path PLH
25
20
ns
tpHL
Propagation delay
Path PLH
2, 5
20
ns
tpLH
Propagation delay
Path HLH
25
15
ns
tpHL
Propagation delay
Path HLH
2, 5
15
ns
tslew
Slew rate
B or Y side outputs
4
0.05
0.4
V/ns
tpHZ
Output enable/
HD to Y or B
3
20
ns
tpZH
disable time
RL = 500
3
20
ns
tDIFF
Propagation delay difference
HD prop tpZH–tpHZ
10
ns
tpHZ
Output enable time
HD to PLHO
3
20
ns
tpZH
Output enable time
RL = 500
20
ns
tpHZ
50
tpZH
Output enable/
Dir to B
RL = 250
Fig 1.
30
ns
tpLZ
disable time
RL = 250
on the B/Y side tP load
50
ns
tpZL
30
tpHZ
1
15
tpZH
Output enable/
Dir to A
Fig 1.
50
ns
tpLZ
disable time
RL = 250
15
ns
tpZL
50
tpHZ
3
6
tpZH
Output enable/
OEA to A
Fig 1.
12
ns
tpLZ
disable time
RL = 250
6
ns
tpZL
12
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