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TDA837x family
Information as of 2000-08-22
TDA837x family; I2C-bus controlled economy PAL/NTSC and NTSC TV-processors
The various versions of the TDA837x series are I2C-bus controlled single-chip TV processors which are intended to be applied in
PAL/NTSC (TDA8374 and TDA8375) and NTSC (TDA8373 and TDA8377) television receivers. All ICs are available in an SDIP56 package
and some versions are also available in a QFP64 package. The ICs are pin compatible so that with one application board NTSC and
PAL/NTSC (or multistandard together with the SECAM decoder TDA8395) receivers can be built. Functionally this IC series is split in to 2
categories:
l
Versions intended to be used in economy TV receivers with all basic functions
l
Versions with additional functions such as E-W geometry control, horizontal and vertical zoom function and YUV interface which are
intended for TV receivers with 110° picture tubes.
Available in all ICs:
l
Vision IF amplifier with high sensitivity and good figures for differential phase and gain
l
PLL demodulator for the IF signal
l
Alignment-free sound demodulator
l
Flexible source selection with a CVBS input for the internal signal and Y/C or CVBS input for the external signal
l
Audio switch
l
The output signal of the CVBS (Y/C) switch is externally available
l
Integrated chrominance trap and band-pass filters (auto-calibrated)
l
Luminance delay line integrated
l
A symmetrical peaking circuit in the luminance channel
l
Black stretching of non-standard CVBS or luminance signals
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