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參數(shù)資料
| 型號： | 935227450557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | TRIPLE, PARALLEL, WORD INPUT LOADING, 0.01 us SETTLING TIME, 10-BIT DAC, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 158K |
| 代理商： | 935227450557 |
1996 Aug 14
7
Philips Semiconductors
Preliminary specication
Triple 10-bit video Digital-to-Analog
Converter (DAC)
TDA8775
Timing (CL = 25 pF); see Fig.4
fclk(max)
maximum clock frequency
SLT = 1; RL = 37.5
50
MHz
SLT = 0; RL = 150
35
MHz
tCPH
clock pulse width HIGH
6
ns
tCPL
clock pulse width LOW
6
ns
tr
clock rise time
4ns
tf
clock fall time
4ns
tSU;DAT
input data set-up time
4
ns
tHD;DAT
input data hold time
2.5
ns
Outputs
OUTB, OUTR AND OUTG ANALOG OUTPUTS (PINS 42, 46 AND 44, REFERENCED TO VSSA) FOR 37.5 LOAD
VOUTmax
maximum output voltage
BLANK and SYNC active
R and B channels
0.714
V
G channel
1.0
V
THD
total harmonic distortion
fi = 4.43 MHz; SLT = 1;
fclk = 50 MHz; RL = 37.5
52
dB
fi = 4.43 MHz; SLT = 0;
fclk = 35 MHz; RL = 150
50
dB
ZL
output load impedance
SLT = 1
tbf
37.5
tbf
SLT = 0
tbf
150
tbf
Transfer function
INL
DC integral non-linearity
±1
±2
LSB
DNL
DC differential non-linearity
±0.7
±1.0
LSB
αct
crosstalk DAC to DAC
tbf
dB
DAC to DAC matching
1.0
tbf
%
Switching characteristics; see Fig.5
td
input to 50% output delay
time
full-scale change;
SLT = 1; RL = 37.5
tbf
ns
full-scale change;
SLT = 0; RL = 150
tbf
ns
ts1
settling time
10 to 90% full-scale change;
SLT = 1; RL = 37.5
4
ns
10 to 90% full-scale change;
SLT = 0; RL = 150
10
ns
ts2
settling time
to
±1 LSB; SLT = 1;
RL = 37.5
tbf
ns
to
±1 LSB; SLT = 0;
RL = 150
tbf
ns
Output transients (glitches)
Vg
area for 1 LSB change
tbf
LSB.ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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